Dispensing with channel estimation: differentially modulated cooperative wireless communications

As a benefit of bypassing the potentially excessive complexity and yet inaccurate channel estimation, differentially encoded modulation in conjunction with low-complexity noncoherent detection constitutes a viable candidate for user-cooperative systems, where estimating all the links by the relays is unrealistic. In order to stimulate further research on differentially modulated cooperative systems, a number of fundamental challenges encountered in their practical implementations are addressed, including the time-variant-channel-induced performance erosion, flexible cooperative protocol designs, resource allocation as well as its high-spectral-efficiency transceiver design. Our investigations demonstrate the quantitative benefits of cooperative wireless networks both from a pure capacity perspective as well as from a practical system design perspective

Coherent receiver design and analysis for interleaved division multiple access (IDMA)

This thesis discusses a new multiuser detection technique for cellular wireless communications. Multiuser communications is critical in cellular systems as multiple terminals (users) transmit to base stations (or wireless infrastructure). Efficient receiver methods are needed to maximise the performance of these links and maximise overall throughput and coverage while minimising inter-cell interference. Recently a new technique, Interleave-Division Multiple Access (IDMA), was developed as a variant of direct-sequence code division multiple access (DS-CDMA). In this new scheme users are separated by user specific interleavers, and each user is allocated a low rate code. As a result, the bandwidth expansion is devoted to the low rate code and not weaker spreading codes. IDMA has shown to have significant performance gains over traditional DS-CDMA with a modest increase in complexity. The literature on IDMA primarily focuses on the design of low rate forward error correcting (FEC) codes, as well as channel estimation. However, the practical aspects of an IDMA receiver such as timing acquisition, tracking, block asynchronous detection, and cellular analysis are rarely studied. The objective of this thesis is to design and analyse practical synchronisation, detection and power optimisation techniques for IDMA systems. It also, for the first time, provides a novel analysis and design of a multi-cell system employing a general multiuser receiver. These tools can be used to optimise and evaluate the performance of an IDMA communication system. The techniques presented in this work can be easily employed for DS-CDMA or other multiuser receiver designs with slight modification. Acquisition and synchronisation are essential processes that a base-station is required to perform before user's data can be detected and decoded. For high capacity IDMA systems, which can be heavily loaded and operate close to the channel capacity, the performance of acquisition and tracking can be severely affected by multiple access interference as well as severe drift. This thesis develops acquisition and synchronisation algorithms which can cope with heavy multiple access interference as well as high levels of drift. Once the timing points have been estimated for an IDMA receiver the detection and decoding process can proceed. An important issue with uplink systems is the alignment of frame boundaries for efficient detection. This thesis demonstrates how a fully asynchronous system can be modelled for detection. This thesis presents a model for the frame asynchronous IDMA system, and then develops a maximum likelihood receiver for the proposed system. This thesis develops tools to analyse and optimise IDMA receivers. The tools developed are general enough to be applied to other multiuser receiver techniques. The conventional EXIT chart analysis of unequal power allocated multiuser systems use an averaged EXIT chart analysis for all users to reduce the complexity of the task. This thesis presents a multidimensional analysis for power allocated IDMA, and shows how it can be utilised in power optimisation. Finally, this work develops a novel power zoning technique for multicell multiuser receivers using the optimised power levels, and illustrates a particular example where there is a 50% capacity improvement using the proposed scheme. -- provided by Candidate

Performance Study of a Near Maximum Likelihood Code-Aided Timing Recovery Technique

International audienceIn this paper, we propose a new code-aided (CA) timing recovery algorithm for various linear constant modulus constellations based on the Maximum Likelihood (ML) estimator. The first contribution is the derivation of a soft estimator expression of the transmitted symbol instead of its true or hard estimated value which is fed into the timing error detector (TED) equation. The proposed expression includes the Log-Likelihood Ratios (LLRs) obtained from a turbo decoder. Our results show that the proposed CA approach achieves almost as good results as the data-aided (DA) approach over a large interval of SNR values while achieving a higher spectral efficiency. We also derive the corresponding CA Cramer Rao Bounds (CRB) for various modulation orders. Contrarily to former work, we develop here the CRB analytical expression for different M-PSK modulation orders and validate them through comparison to empirical CRB obtained by Monte Carlo iterations. The proposed CA estimator realizes an important gain over the non data-aided approach (NDA) and achieves a smaller gap when compared to its relative CA CRB, especially at moderate SNR values where modern systems are constrained to work

Top down, bottom up structured programming and program structuring

New design and programming techniques for shuttle software. Based on previous Apollo experience, recommendations are made to apply top-down structured programming techniques to shuttle software. New software verification techniques for large software systems are recommended. HAL, the higher order language selected for the shuttle flight code, is discussed and found to be adequate for implementing these techniques. Recommendations are made to apply the workable combination of top-down, bottom-up methods in the management of shuttle software. Program structuring is discussed relevant to both programming and management techniques

Irregular repetition code hybrid ARQ in wireless system

Error control consists of error detection and error correction in the communication system. The purpose of this research work is to reduce error in the wireless communication system by using the advantages of both error correction techniques which are forward error correction (FEC) and automatic repeat request (ARQ). Thus, error can be corrected without retransmission and also via retransmission(s) when needed. Combination of FEC and ARQ is known as Hybrid ARQ. In this paper, Hybrid ARQ system is designed using three components which are the irregular repetition code (IRC) as a simple code, bit-interleaved coded modulation with iterative decoding (BICM-ID) as a simple Turbo processing and ARQ. The HARQ system is enhanced by the extended mapping (EM) adopted in the mapping system. The performance of the systems is evaluated in the additive white Gaussian noise (AWGN). The results show the Hybrid ARQ with extended mapping (Hybrid ARQ-EM) outperforms Hybrid ARQ with standard mapping (Hybrid ARQ-SM). Hybrid ARQ-EM achieves low bit error rate BER (10-5) at low signal-to-noise ratio SNR which only 3.03dB close to the theoretical limit. The proposed system Hybrid ARQ-EM achieves 52 percent gain enhancement of SNR gap from the theoretical limit compared to Hybrid ARQ-SM. Hybrid ARQ-EM gives better performance although in worse channel condition

Low-complexity soft-decision feedback turbo equalization for multilevel modulations

This dissertation proposes two new decision feedback equalization schemes suitable for multilevel modulation systems employing turbo equalization. One is soft-decision feedback equalization (SDFE) that takes into account the reliability of both soft a priori information and soft decisions of the data symbols. The proposed SDFE exhibits lower signal to noise ratio (SNR) threshold that is required for water fall bit error rate (BER) and much faster convergence than the near-optimal exact minimum mean square error linear equalizer (Exact-MMSE-LE) for high-order constellation modulations. The proposed SDFE also offers a low computational complexity compared to the Exact-MMSE-LE. The drawback of the SDFE is that its coefficients cannot reach the matched filter bound (MFB) and therefore after a large number of iterations (e.g. 10), its performance becomes inferior to that of the Exact-MMSE-LE. Therefore, soft feedback intersymbol interference (ISI) canceller-based (SIC) structure is investigated. The SIC structure not only exhibits the same low complexity, low SNR threshold and fast convergence as the SDFE but also reaches the MFB after a large number of iterations. Both theoretical analysis and numerical simulations demonstrate why the SIC achieves MFB while the SDFE cannot. These two turbo equalization structures are also extended from single-input single-output (SISO) systems to multiple-input multiple-output (MIMO) systems and applied in high data-rate underwater acoustic (UWA) communications --Abstract, page iv

Expander selection for an on board ORC energy recovery system

This paper deals with the comparison between volumetric expanders (screw, scroll and rotary vane) and an Inlet Forward Radial (IFR) micro turbine for the exploitation of an on board Organic Rankine Cycle (ORC) energy recovery system. The sensible heat recovered from a common bus engine (typically 8000cc) feeds the energy recovery system that can generate sufficient extra power to sustain the air-conditioning system and part of the auxiliaries. The concept is suitable for all kind of thermally propelled vehicles, but the application considered here is specific for an urban bus. The ORC cycle performance is calculated by a Process Simulator (CAMEL Pro) and the results are discussed. A preliminary design of the considered expanders is proposed using ad-hoc made models implemented in MATLAB; the technical constraints inherent to each machine are listed in order to perform the optimal choice of the expander based on efficiency, reliability and power density. Last step will be the selection of the expander that suites the specific technical and design requests. The final choice relapsed on the screw motor, for it is the best compromise in terms of efficiency, lubrication and reliability

Sparse Message Passing Based Preamble Estimation for Crowded M2M Communications

Due to the massive number of devices in the M2M communication era, new challenges have been brought to the existing random-access (RA) mechanism, such as severe preamble collisions and resource block (RB) wastes. To address these problems, a novel sparse message passing (SMP) algorithm is proposed, based on a factor graph on which Bernoulli messages are updated. The SMP enables an accurate estimation on the activity of the devices and the identity of the preamble chosen by each active device. Aided by the estimation, the RB efficiency for the uplink data transmission can be improved, especially among the collided devices. In addition, an analytical tool is derived to analyze the iterative evolution and convergence of the SMP algorithm. Finally, numerical simulations are provided to verify the validity of our analytical results and the significant improvement of the proposed SMP on estimation error rate even when preamble collision occurs.Comment: submitted to ICC 2018 with 6 pages and 4 figure

Lagrangian relaxation-based multi-threaded discrete gate sizer

In integrated circuit design gate sizing is one of the key optimization techniques which is repeatedly invoked to trade-off delays for area and/or power of the gates during logic design and physical design stages. With increasing design sizes of a million gates and larger, discrete gate sizes and non-convex delay models the gate sizing algorithms that were designed for continuous sizes and convex delay models are slow and timing inaccurate. Of the several published discrete gate sizing algorithms, recent works have shown that Lagrangian relaxation based gate sizers have produced designs with the lowest power on average with high timing accuracy. But they are also very slow due to a large number of expensive timing updates spread across hundreds of iterations of solving the Lagrangian sub-problem. In this thesis we present a Lagrangian relaxation based multi-threaded discrete gate sizer for fast timing and power reduction by swapping the gate sizes and the threshold voltages. We developed two parallelization enabling techniques to reduce the runtime of Lagrangian sub-problem solver, namely, mutual exclusion edge (MEE) assignment and directed acyclic graph (DAG) based netlist traversal. MEEs are dummy edges assigned to reduce computational dependencies among gates sharing one or more common fan-ins. DAG based netlist traversal facilitates simultaneous resizing of gates belonging to different topological levels. We designed a Lagrange multiplier update framework that enables rapid convergence of the timing recovery and power recovery algorithms. To reduce the runtime of timing updates, we proposed a simple and fast-to-compute effective capacitance model and several mechanisms to calibrate the timing models to improve their accuracy. Compared to the state-of-the-art gate sizer, our proposed gate sizer is on average 15x faster and the optimized designs have only 1.7\% higher power. In digital synchronous designs simultaneous gate sizing and clock skew scheduling provides significantly more power saving. We extend the gate sizer to simultaneously schedule the clock skew. It can achieve an average of 18.8\% more reduction in power with only 20\% increase in the runtime