Field coupled electrostatic discharge sensitivity database

Electrostatic Discharge (ESD) can disrupt the performance of an electronic system, like an MP3 player either by injected currents or by transient fields. It is possible to predict at least the approximate transient field levels inside a system, but it is difficult to determine the response of ICs subjected to these fields, as no IC specific data is available, and as it is often too involved to measure the sensitivity of every IC possibly used in a product. As deterministic solutions are difficult to achieve, a statistical approach has been selected in this research. The goal of this database for field coupled ESD (Electrostatic Discharge) sensitivity is to give guidance on estimating if soft-error (e.g., resets) problems are likely to occur, for a given ESD scenario. Electric field probes, magnetic field probes, and the ΣΔ probe, which can inject either electrical fields or magnetic fields as desired, are designed as field injection devices for the project. A TEM cell and an IC-stripline, which are designed for high voltage immunity testing, are also developed as injection methods for the purpose of the IC measurements for this database. The measurement setups for the off-shelf electronic products using the probes are shown. Further detailing parameter dependence, a 1.2 mm spacer and a 100 MHz low pass were inserted into the test setups. Observing the crash levels of the ICs under varying conditions allows better insight into the mechanism and the robustness of the database with respect to uncertainties introduced by the field injection methods and their calibrations. In the end, the data from 37 real ICs are analyzed and discussed, and the examples of applications for the database are also discussed --Abstract, page iii

Optimization of ESD Protection Methods in Electronics Assembly Based on Process and Product Specific Risks

The last 40 years has seen significant development in electrical component and system technologies. However, advances with semiconductor technologies, cost optimizations, and die area shrinking have made electronics more sensitive to excess electrical stress and electromagnetic disturbances. In this dissertation work, one of these stress scenarios is studied: electrostatic discharge (ESD) risks in the electronics assembly process environment. In the assembly process, single electrical components, circuit boards, and different subassemblies are assembled together, tested, and programmed to complete fully functional electrical products.A noncontrolled electronics assembly environment produces unpredictable ESD risks and causes yield losses. Therefore, it is necessary to protect electronics against ESD during handling and manufacturing. This is accomplished with the aid of an electrostatic protected area (EPA) and an ESD control program plan, which are typically built according to IEC61340-5-1-2007 and ANSI S20.20-2014 standards. These two standards define how to design, establish, implement, and maintain the program with administrative and technical requirements. Here, a 100 V human body model (HBM) limit is currently used as the base for building EPAs and ESD control programs. However, current ESD control programs are not always able to prevent ESD damages in EPA. On top of actual ESD events, there can be electromagnetic interference (EMI) initiated product and equipment disturbances in well-built EPAs.In this research work, the main focus is on additional ESD control methods that go beyond the specifications and requirements of the IEC61340-5-1 and ANSI/ESD S20.20 standards. The objective is to optimize ESD protection methods based on real ESD risk scenarios found during PCB assembly, testing, handling, and during system final assembly to achieve close to zero-failure level. At the same time, the objective is to optimize ESD control-related costs in the process area.Based on the research, the focus of the additional ESD and EMI control methods should be with final assembly, programming, and testing process phases where about 90% observed failure and disturbance cases have occurred. Therefore, in an improved ESD control program, EMI control, controlling product part and cable charging are added into the program, together with groundings and other basic controlled EPA items. The charging of product parts should be monitored with potential, discharge current and charge meters, and that data should be used together with process analysis to detect all known ESD risk scenarios. The sensitivity of subassemblies should be tested, for example, by using a charged board event (CBE), field collapse event (FCE), and cable discharge event (CDE) methods that simulate real world ESD scenarios found in the process area. This gives more accurate data for risk assessments than an electrical-component-specific HBM or charged device model (CDM) qualification data.The proposed additional control methods were implemented in more than 10 large electronics assembly facilities, resulting in a significant reduction in ESD-related failures and disturbance-related process yield challenges. Therefore, as a future work, product and process specific ESD and EMI risk should be emphasized in ESDcontrol-related trainings, standards, standard practices, and technical reports

NASA Space Engineering Research Center Symposium on VLSI Design

The NASA Space Engineering Research Center (SERC) is proud to offer, at its second symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories and the electronics industry. These featured speakers share insights into next generation advances that will serve as a basis for future VLSI design. Questions of reliability in the space environment along with new directions in CAD and design are addressed by the featured speakers

Minutes of the CD-ROM Workshop

The workshop described in this document had two goals: (1) to establish guidelines for the CD-ROM as a tool to distribute datasets; and (2) to evaluate current scientific CD-ROM projects as an archive. Workshop attendees were urged to coordinate with European groups to develop CD-ROM, which is already available at low cost in the U.S., as a distribution medium for astronomical datasets. It was noted that NASA has made the CD Publisher at the National Space Science Data Center (NSSDC) available to the scientific community when the Publisher is not needed for NASA work. NSSDC's goal is to provide the Publisher's user with the hardware and software tools needed to design a user's dataset for distribution. This includes producing a master CD and copies. The prerequisite premastering process is described, as well as guidelines for CD-ROM construction. The production of discs was evaluated. CD-ROM projects, guidelines, and problems of the technology were discussed

Device and Circuit Level EMI Induced Vulnerability: Modeling and Experiments

Electro-magnetic interference (EMI) commonly exists in electronic equipment containing semiconductor-based integrated circuits (ICs). Metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the ICs may be disrupted under EMI conditions due to transient voltage-current surges, and their internal states may change undesirably. In this work, the vulnerabilities of silicon MOSFETs under EMI are studied at the device and the circuit levels, categorized as non-permanent upsets (``Soft Errors'') and permanent damages (``Hard Failures''). The Soft Errors, such as temporary bit errors and waveform distortions, may happen or be intensified under EMI, as the transient disruptions activate unwanted and highly non-linear changes inside MOSFETs, such as Impact Ionization and Snapback. The system may be corrected from the erroneous state when the EMI condition is removed. We simulate planar silicon n-type MOSFETs at the device level to study the physical mechanisms leading to or complicate the short-term, signal-level Soft Errors. We experimentally tested commercially available MOSFET devices. Not included in regular MOSFET models, exponential-like current increases as the terminal voltage increases are observed and explained using the device-level knowledge. We develop a compact Soft Error model, compatible with circuit simulators using lumped (or compact-model) components and closed-form expressions, such as SPICE, and calibrate it with our in-house experimental data using an in-house extraction technique based on the Genetic Algorithm. Example circuits are simulated using the extracted device model and under EMI-induced transient disruptions. The EMI voltage-current disruptions may also lead to permanent Hard Failures that cannot be repaired without replacement. One type of Hard Failures, the MOSFET gate dielectric (or ``oxide'') breakdown, can result in input-output relation changes and additional thermal runaway. We have fabricated individual MOSFET devices at the FabLab at the University of Maryland NanoCenter. We experimentally stress-test the fabricated devices and observe the rapid, permanent oxide breakdown. Then, we simulate a nano-scale FinFET device with ultra-thin gate oxide at the device level. Then, we apply the knowledge from our experiments to the simulated FinFET, producing a gate oxide breakdown Hard Failure circuit model. The proposed workflow enables the evaluation of EMI-induced vulnerabilities in circuit simulations before actual fabrication and experiments, which can help the early-stage prototyping process and reduce the development time

Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved

Resistive-RAM for Data Storage Applications.

Mainstream non-volatile memory technology, dominated by the floating gate transistor, has historically improved in density, performance and cost primarily by means of process scaling. This simple geometrical scaling now faces significant challenges due to constraints of electrostatics and reliability. Thus, novel non-transistor based memory paradigms are being widely explored. Among the various contenders for next generation storage technology, RRAM devices have got immense attention due to their high-speed, multilevel capability, scalability, simple structure, low voltage operation and high endurance. In this thesis, electrical and material characterization is carried out on a MIM device system and formation / annihilation of nanoscale filaments is shown to be the reason behind the resistance switching. The MIM system is optimized to include an in-cell resistor which is shown to improve device endurance and reduce stuck-at-one faults. For highest density, the devices were arranged in a crossbar geometry and vertically integrated on CMOS decoders to demonstrate the feasibility of practical data storage applications. Next, we show that these binary RRAM devices exhibit native stochastic nature of resistive switching. Even for a fixed voltage on the same device, the wait time associated with programming is not fixed and is random and broadly distributed. However, the probability of switching can be predicted and controlled by the programming pulse. These binary devices have been used to generate random bit-streams with predicable bias ratios in time and space domains. The ability to produce random bit-streams using binary resistive switching devices based on the native stochastic switching principle may potentially lead to novel non-von-Neumann computing paradigms. Further, sub-1nA operating current devices have been developed. This ultra-low current provides energy savings by minimizing programming, erase and read currents. Despite having such low currents, excellent retention, on/off ratio and endurance have been demonstrated. Finally a scalable approach to simple 3D stacking is discussed. By implementation of a vertical sidewall-based architecture, the number of critical lithography steps can be reduced. A vertical device structure based on a W / WOx / Pd material system is developed. This scalable architecture is well suited for development of analog memory and neuromorphic systems.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110461/1/sidgaba_1.pd

NASA Tech Briefs, February 1999

Topics: Test and Measurement; Electronic Components and Circuits; Electronic Systems; Materials; Computer Software; Mechanics; Machinery/Automation; Physical Sciences; Computers and Peripherals

Simulation der Zerstörwirkung von elektrostatischen Entladungen (ESD) auf Kfz-Elektroniksysteme

Die Eigenschaften von elektrostatischen Entladungen stellen ein erhebliches Störpotential für elektronische Bauelemente und Geräte dar. Es sind daher Maßnahmen notwendig um empfindliche Bauelemente zu schützen. Im Rahmen dieser Arbeit wurde eine Simulationsmethode erarbeitet, welche es erlaubt, die leitungsgebundene Auswirkung von transienten Pulsen auf Kfz-Elektroniksystemen zu analysieren und zu bewerten. Der Simulationsansatz kann dazu verwendet werden um ESD-Schutzstrategien in Kfz-System zu beurteilen, die dafür notwendigen Komponenten zu dimensionieren und die dabei entstehenden Phänomene und Effekte zu analysieren. Mit den dabei erstellten Modellen ist es möglich, sowohl das elektrische Verhalten als auch die Ausfallschwelle der belasteten Systeme mittels gängiger Simulatoren zu ermitteln. Die dabei erarbeiteten Verfahren zur Modellierung der einzelnen Komponenten erlauben es das ESD Verhalten der betrachteten Systeme mit einem vertretbaren Modellierungsaufwand zu bewerten. Hierbei konnte unter anderem ein Ansatz entwickelt werden, welcher das nichtlineare Verhalten von ESD- Schutzkomponenten und IC-Eingängen unter Pulsbelastung beschreibt. Darauf aufbauend wurde ein thermisches Ausfallmodell entwickelt. Bei der Erstellung der Verfahren wurde darauf geachtet, dass alle notwendigen Modellparameter mithilfe von Messungen ermittelt werden können. Dies gilt sowohl für das nichtlineare Verhalten von diskreten Bauelementen, als auch für die Parameter zur Beschreibung des Verhaltens von IC-Eingängen unter Pulsbelastung und die darauf aufbauenden thermischen Ausfallmodelle