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Data reliability and error correction for NAND Flash Memory System
NAND flash memory has been widely used for data storage due to its high density, high throughput, and low power. However, as the flash memory scales to smaller process technologies and stores more bits per cell, its reliability is decreasing. The error correction coding can be used to significantly improve the data reliability; nevertheless, the advanced ECCs such as low-density parity-check (LDPC) codes generally demand soft decisions while NAND flash memory channel provides hard-decisions only. Extracting the soft information requires the accurate characterization of flash memory channel and the effective design of coding schemes.
To this end, we have presented a novel LDPC-TCM coding scheme for the Multilevel Cell (MLC) flash memories. The a posteriori TCM decoding algorithm is used in the scheme to generate soft information, which is fed to the LDPC decoder for further correction of data bits. It has been demonstrated that the proposed scheme can achieve higher error correction performance than the traditional hard-decisions based flash coding algorithms, and is feasible in the design practice. Further with the LDPC-TCM, we believe it is important to characterize the flash memory channel and investigate a method to calculate the soft decision for each bit, with the available channel outputs. We studied the various noises and interferences occurring in the memory channel and mathematically formulated the probability density function of the overall noise distribution. Based on the results we derived the final distribution for the cell threshold voltages, which can be used to instruct the calculation of soft decisions. The discoveries on the theoretical level have been demonstrated to be consistent with the real channel behaviours. The channel characterization and model provided in this dissertation can enable more design of soft-decisions based ECCs for future NAND flash memories.
The data pattern processing algorithm deals with the write patterns and targets to lower the proportion of patterns that would introduce data errors. On the other hand, the voltages applied to the memory cells charges the MOSFET capacitances frequently on programming these data patterns, leading to the power problem. The high energy consumption and current spikes also cause reliability issue to the data stored in the flash memory. This dissertation proposes a write pattern formatting algorithm (WPFA) attempting to solve the two problems together. We have designed and implemented the algorithm and evaluated its performance through both the software simulations and hardware synthesis
๋ธ๋ํ๋์ ๋ฉ๋ชจ๋ฆฌ ์ค๋ฅ์ ์ ์ ์ํ ๊ณ ์ฑ๋ฅ LDPC ๋ณตํธ๋ฐฉ๋ฒ ์ฐ๊ตฌ
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ)-- ์์ธ๋ํ๊ต ๋ํ์ : ์ ๊ธฐยท์ปดํจํฐ๊ณตํ๋ถ, 2013. 8. ์ฑ์์ฉ.๋ฐ๋์ฒด ๊ณต์ ์ ๋ฏธ์ธํ์ ๋ฐ๋ผ ๋นํธ ์๋ฌ์จ์ด ์ฆ๊ฐํ๋ ๋ธ๋ ํ๋์ ๋ฉ๋ชจ๋ฆฌ์์ ๊ณ ์ฑ๋ฅ ์๋ฌ ์ ์ ๋ฐฉ๋ฒ์ ํ์์ ์ด๋ค. Low-density parity-check (LDPC) ๋ถํธ์ ๊ฐ์ ์ฐํ์ ์๋ฌ ์ ์ ๋ถํธ๋ ๋ฐ์ด๋ ์๋ฌ ์ ์ ์ฑ๋ฅ์ ๋ณด์ด์ง๋ง, ๋์ ๊ตฌํ ๋ณต์ก๋๋ก ์ธํด ํ๋์ ๋ฉ๋ชจ๋ฆฌ ์์คํ
์ ์ ์ฉ๋๊ธฐ ํ๋ ๋จ์ ์ด ์๋ค. ๋ณธ ๋
ผ๋ฌธ์์๋ LDPC ๋ถํธ์ ํจ์จ์ ์ธ ๋ณตํธ๋ฅผ ์ํด ๊ณ ์ฑ๋ฅ ๋ฉ์์ง ์ ํ ์ค์ผ์ค๋ง ๋ฐฉ๋ฒ๊ณผ ์ ๋ณต์ก๋ ๋ณตํธ ์๊ณ ๋ฆฌ์ฆ์ ์ ์ํ๋ค. ํนํ finite geometry (FG) LDPC ๋ถํธ์ ๋ํ ํจ์จ์ ์ธ ๋์ฝ๋ ์ํคํ
์ณ๋ฅผ ์ ์ํ๋ฉฐ, ๊ตฌํ๋ ๋์ฝ๋๋ฅผ ์ด์ฉํ์ฌ ๋ธ๋ ํ๋์ ๋ฉ๋ชจ๋ฆฌ์ ๋ํด ์ฐํ์ ๋ณตํธ์์ ์๋์ง ์๋ชจ๋์ ๋ํด ์ฐ๊ตฌํ๋ค.
๋ณธ ๋
ผ๋ฌธ์ ์ฒซ ๋ฒ์งธ ๋ถ๋ถ์์๋ ๋์ ์ค์ผ์ค๋ง (informed dynamic scheduling, IDS) ์๊ณ ๋ฆฌ์ฆ์ ์ฑ๋ฅํฅ์ ๋ฐฉ๋ฒ์ ๋ํด ์ฐ๊ตฌํ๋ค. ์ด๋ฅผ ์ํด ์ฐ์ ๊ธฐ์กด์ ๊ฐ์ฅ ๋น ๋ฅธ ์๋ ด ์๋๋ฅผ ๋ณด์ด๋ IDS ์๊ณ ๋ฆฌ์ฆ์ธ ๋ ์ง๋์ผ ์ ๋ขฐ ์ ํ (residual belief propagation, RBP) ์๊ณ ๋ฆฌ์ฆ์ ๋์ ํน์ฑ์ ๋ถ์ํ๊ณ , ์ด๋ฅผ ๋ฐํ์ผ๋ก ํน์ ๋
ธ๋์ ๋ฉ์์ง ๊ฐฑ์ ์ด ์ง์ค๋๋ ๊ฒ์ ๋ฐฉ์งํ์ฌ RBP ์๊ณ ๋ฆฌ์ฆ์ ์๋ ด์๋๋ฅผ ์ฆ๊ฐ์ํจ improved RBP (iRBP) ์๊ณ ๋ฆฌ์ฆ์ ์ ์ํ๋ค. ๋ํ iRBP์ ๋ฐ์ด๋ ์๋ ด์๋์ ๊ธฐ์กด์ NS ์๊ณ ๋ฆฌ์ฆ์ ์ฐ์ํ ์๋ฌ ์ ์ ๋ฅ๋ ฅ์ ๋ชจ๋ ๊ฐ์ถ ์ ๋๋กฌ ๊ธฐ๋ฐ์ ํผํฉ ์ค์ผ์ค๋ง (mixed scheduling) ๋ฐฉ๋ฒ์ ์ ์ํ๋ค. ๋์ผ๋ก ๋ค์ํ ๋ถํธ์จ์ LDPC ๋ถํธ์ ๋ํ ๋ชจ์์คํ์ ํตํด ์ ์๋ ์ ๋๋กฌ ๊ธฐ๋ฐ์ ํผํฉ ์ค์ผ์ค๋ง ๋ฐฉ๋ฒ์ด ๋ณธ ๋
ผ๋ฌธ์์ ์ํ๋ ๋ค๋ฅธ ๋ชจ๋ ์ค์ผ์ค๋ง ์๊ณ ๋ฆฌ์ฆ์ ์ฑ๋ฅ์ ๋ฅ๊ฐํจ์ ํ์ธํ์๋ค.
๋
ผ๋ฌธ์ ๋ ๋ฒ์งธ ๋ถ๋ถ์์๋ ๋ณตํธ ์คํจ์ ๋ง์ ๋นํธ ์๋ฌ๋ฅผ ๋ฐ์์ํค๋ a posteriori probability (APP) ์๊ณ ๋ฆฌ์ฆ์ ๊ฐ์ ๋ฐฉ์์ ๋ฐฉ์์ ์ ์ํ๋ค. ๋ํ ๋น ๋ฅธ ์๋ ด์๋์ ์ฐ์ํ ์๋ฌ ๋ง๋ฃจ (error-floor) ์ฑ๋ฅ์ผ๋ก ๋ฐ์ดํฐ ์ ์ฅ์ฅ์น์ ์ ํฉํ FG-LDPC ๋ถํธ์ ๋ํด ์ ์๋ ์๊ณ ๋ฆฌ์ฆ์ด ์ ์ฉ๋ ํ๋์จ์ด ์ํคํ
์ฒ๋ฅผ ์ ์ํ์๋ค. ์ ์๋ ์ํคํ
์ฒ๋ ๋์ ๋
ธ๋ ๊ฐ์ค์น๋ฅผ ๊ฐ์ง๋ FG-LDPC ๋ถํธ์ ์ ํฉํ๋๋ก ์ฌํํธ ๋ ์ง์คํฐ (shift registers)์ SRAM ๊ธฐ๋ฐ์ ํผํฉ ๊ตฌ์กฐ๋ฅผ ์ฑ์ฉํ๋ฉฐ, ๋์ ์ฒ๋ฆฌ๋์ ์ป๊ธฐ ์ํด ํ์ดํ๋ผ์ธ๋ ๋ณ๋ ฌ ์ํคํ
์ฒ๋ฅผ ์ฌ์ฉํ๋ค. ๋ํ ๋ฉ๋ชจ๋ฆฌ ์ฌ์ฉ๋์ ์ค์ด๊ธฐ ์ํด ์ธ ๊ฐ์ง์ ๋ฉ๋ชจ๋ฆฌ ์ฉ๋ ๊ฐ์ ๊ธฐ๋ฒ์ ์ ์ฉํ๋ฉฐ, ์ ๋ ฅ ์๋น๋ฅผ ์ค์ด๊ธฐ ์ํด ๋ ๊ฐ์ง์ ์ ์ ๋ ฅ ๊ธฐ๋ฒ์ ์ ์ํ๋ค. ๋ณธ ์ ์๋ ์ํคํ
์ฒ๋ ๋ถํธ์จ 0.96์ (68254, 65536) Euclidean geometry LDPC ๋ถํธ์ ๋ํด 0.13-um CMOS ๊ณต์ ์์ ๊ตฌํํ์๋ค.
๋ง์ง๋ง์ผ๋ก ๋ณธ ๋
ผ๋ฌธ์์๋ ์ฐํ์ ๋ณตํธ๊ฐ ์ ์ฉ๋ ๋ธ๋ ํ๋์ ๋ฉ๋ชจ๋ฆฌ ์์คํ
์ ์๋์ง ์๋ชจ๋ฅผ ๋ฎ์ถ๋ ๋ฐฉ๋ฒ์ ๋ํด ์ ์ํ๋ค. ์ฐํ์ ๊ธฐ๋ฐ์ ์๋ฌ ์ ์ ์๊ณ ๋ฆฌ์ฆ์ ๋์ ์ฑ๋ฅ์ ๋ณด์ด์ง๋ง, ์ด๋ ํ๋์ ๋ฉ๋ชจ๋ฆฌ์ ์ผ์ฑ ์์ ์๋์ง ์๋ชจ๋ฅผ ์ฆ๊ฐ ์ํค๋ ๋จ์ ์ด ์๋ค. ๋ณธ ์ฐ๊ตฌ์์๋ ์์ ๊ตฌํ๋ LDPC ๋์ฝ๋๊ฐ ์ฑ์ฉ๋ ๋ธ๋ ํ๋์ ๋ฉ๋ชจ๋ฆฌ ์์คํ
์ ์๋์ง ์๋ชจ๋ฅผ ๋ถ์ํ๊ณ , LDPC ๋์ฝ๋์ BCH ๋์ฝ๋ ๊ฐ์ ์นฉ ์ฌ์ด์ฆ์ ์๋์ง ์๋ชจ๋์ ๋น๊ตํ์๋ค. ์ด์ ๋๋ถ์ด ๋ณธ ๋
ผ๋ฌธ์์๋ LDPC ๋์ฝ๋๋ฅผ ์ด์ฉํ ์ผ์ฑ ์ ๋ฐ๋ ๊ฒฐ์ ๋ฐฉ๋ฒ์ ์ ์ํ๋ค. ๋ณธ ์ฐ๊ตฌ๋ฅผ ํตํด ์ ์๋ ๋ณตํธ ๋ฐ ์ค์ผ์ค๋ง ์๊ณ ๋ฆฌ์ฆ, VLSI ์ํคํ
์ณ, ๊ทธ๋ฆฌ๊ณ ์ฝ๊ธฐ ์ ๋ฐ๋ ๊ฒฐ์ ๋ฐฉ๋ฒ์ ํตํด ๋ธ๋ ํ๋์ ๋ฉ๋ชจ๋ฆฌ ์์คํ
์ ์๋ฌ ์ ์ ์ฑ๋ฅ์ ๊ทน๋ํ ํ๊ณ ์๋์ง ์๋ชจ๋ฅผ ์ต์ํ ํ ์ ์๋ค.High-performance error correction for NAND flash memory is greatly needed because the raw bit error rate increases as the semiconductor geometry shrinks for high density. Soft-decision error correction, such as low-density parity-check (LDPC) codes, offers high performance but their implementation complexity hinders wide adoption to consumer products. This dissertation proposes two high-performance message-passing schedules and a low-complexity decoding algorithm for LDPC codes. In particular, an efficient decoder architecture for finite geometry (FG) LDPC codes is proposed, and the energy consumption of soft-decision decoding for NAND flash memory is analyzed.
The first part of this dissertation is devoted to improving the informed dynamic scheduling (IDS) algorithms. We analyze the behavior of the residual belief propagation (RBP), which is the fastest IDS algorithm, and develop an improved RBP (iRBP) by avoiding the concentration of message updates at a particular node. We also study the syndrome-based mixed scheduling of the iRBP and the node-wise scheduling (NS). The proposed mixed scheduling outperforms all other scheduling methods tested in this work.
The next part of this dissertation is to develop a conditional variable node update scheme for the a posteriori probability (APP) algorithm. The developed algorithm is robust to decoding failures and can reduce the dynamic power consumption by lowering switching activities in the LDPC decoder. To implement the developed algorithm, we propose a memory-efficient pipelined parallel architecture for LDPC decoding. The architecture employs FG-LDPC codes that not only show fast convergence speed and good error-floor performance but also perform well with iterative decoding algorithms, which is especially suitable for data storage devices. We also developed a rate-0.96 (68254, 65536) Euclidean geometry LDPC code and implemented the proposed architecture in 0.13-um CMOS technology.
This dissertation also covers low-energy error correction of NAND flash memory through soft-decision decoding. The soft-decision-based error correction algorithms show high performance, but they demand an increased number of flash memory sensing operations and consume more energy for memory access. We examine the energy consumption of a NAND flash memory system equipping an LDPC code-based soft-decision error correction circuit. The sum of energy consumed at NAND flash memory and the LDPC decoder is minimized. In addition, the chip size and energy consumption of the decoder were compared with those of two Bose-Chaudhuri-Hocquenghem (BCH) decoding circuits showing the comparable error performance and the throughput. We also propose an LDPC decoder-assisted precision selection method that needs virtually no overhead. This dissertation is intended to develop high-performance and low-power error correction circuits for NAND flash memory by studying improved decoding and scheduling algorithms, VLSI architecture, and a read precision selection method.1 Introduction 1
1.1 NAND Flash Memory 1
1.2 LDPC Codes 4
1.3 Outline of the Dissertation 6
2 LDPC Decoding and Scheduling Algorithms 8
2.1 Introduction 8
2.2 Decoding Algorithms for LDPC Codes 10
2.2.1 Belief Propagation Algorithm 10
2.2.2 Simplified Belief Propagation Algorithms 12
2.3 Message-Passing Schedules for Decoding of LDPC Codes 15
2.3.1 Static Schedules 15
2.3.2 Dynamic Schedules 17
3 Improved Dynamic Scheduling Algorithms for Decoding of LDPC Codes 22
3.1 Introduction 22
3.2 Improved Residual Belief Propagation Algorithm 23
3.3 Syndrome-Based Mixed Scheduling of iRBP and NS 26
3.4 Complexity Analysis and Simulation Results 28
3.4.1 Complexity Analysis 28
3.4.2 Simulation Results 29
3.5 Concluding Remarks 33
4 A Pipelined Parallel Architecture for Decoding of Finite-Geometry LDPC Codes 36
4.1 Introduction 36
4.2 Finite-Geometry LDPC Codes and Conditional Variable Node Update Algorithm 38
4.2.1 Finite-Geometry LDPC codes 38
4.2.2 Conditional Variable Node Update Algorithm for Fixed-Point Normalized APP-Based Algorithm 40
4.3 Decoder Architecture 46
4.3.1 Baseline Sequential Architecture 46
4.3.2 Pipelined-Parallel Architecture 54
4.3.3 Memory Capacity Reduction 57
4.4 Implementation Results 60
4.5 Concluding Remarks 64
5 Low-Energy Error Correction of NAND Flash Memory through Soft-Decision Decoding 66
5.1 Introduction 66
5.2 Energy Consumption of Read Operations in NAND Flash Memory 67
5.2.1 Voltage Sensing Scheme for Soft-Decision Data Output 67
5.2.2 LSB and MSB Concurrent Access Scheme for Low-Energy Soft-Decision Data Output 72
5.2.3 Energy Consumption of Read Operations in NAND Flash Memory 73
5.3 The Performance of Soft-Decision Error Correction over a NAND Flash Memory Channel 76
5.4 Hardware Performance of the (68254, 65536) LDPC Decoder 81
5.4.1 Energy Consumption of the LDPC Decoder 81
5.4.2 Performance Comparison of the LDPC Decoder and Two BCH Decoders 83
5.5 Low-Energy Error Correction Scheme for NAND Flash Memory 87
5.5.1 Optimum Precision for Low-Energy Decoding 87
5.5.2 Iteration Count-Based Precision Selection 90
5.6 Concluding Remarks 91
6 Conclusion 94
Bibliography 96
Abstract in Korean 110
๊ฐ์ฌ์ ๊ธ 112Docto
Flash Memory Devices
Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today โ3Dโ means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement
Algorithms and Data Representations for Emerging Non-Volatile Memories
The evolution of data storage technologies has been extraordinary. Hard disk drives
that fit in current personal computers have the capacity that requires tons of transistors
to achieve in 1970s. Today, we are at the beginning of the era of non-volatile memory
(NVM). NVMs provide excellent performance such as random access, high I/O speed, low
power consumption, and so on. The storage density of NVMs keeps increasing following
Mooreโs law. However, higher storage density also brings significant data reliability issues.
When chip geometries scale down, memory cells (e.g. transistors) are aligned much closer
to each other, and noise in the devices will become no longer negligible. Consequently,
data will be more prone to errors and devices will have much shorter longevity.
This dissertation focuses on mitigating the reliability and the endurance issues for two
major NVMs, namely, NAND flash memory and phase-change memory (PCM). Our main
research tools include a set of coding techniques for the communication channels implied
by flash memory and PCM. To approach the problems, at bit level we design error
correcting codes tailored for the asymmetric errors in flash and PCM, we propose joint
coding scheme for endurance and reliability, error scrubbing methods for controlling storage
channel quality, and study codes that are inherently resisting to typical errors in flash
and PCM; at higher levels, we are interested in analyzing the structures and the meanings
of the stored data, and propose methods that pass such metadata to help further improve
the coding performance at bit level. The highlights of this dissertation include the first
set of write-once memory code constructions which correct a significant number of errors,
a practical framework which corrects errors utilizing the redundancies in texts, the first
report of the performance of polar codes for flash memories, and the emulation of rank
modulation codes in NAND flash chips
Energy-Efficient Decoders of Near-Capacity Channel Codes.
Channel coding has become essential in state-of-the-art communication and storage systems for ensuring reliable transmission and storage of information. Their goal is to achieve high transmission reliability while keeping the transmit energy consumption low by taking advantage of the coding gain provided by these codes. The lowest total system energy is achieved with a decoder that provides both good coding gain and high energy-efficiency. This thesis demonstrates the VLSI implementation of near-capacity channel decoders using the LDPC, nonbinary LDPC (NB-LDPC) and polar codes with an emphasis of reducing the decode energy.
LDPC code is a widely used channel code due to its excellent error-correcting performance. However, memory dominates the power of high-throughput LDPC decoders. Therefore, these memories are replaced with a novel non-refresh embedded DRAM (eDRAM) taking advantage of the deterministic memory access pattern and short access window of the decoding algorithm to trade off retention time for faster access speed. The resulting LDPC decoder with integrated eDRAMs achieves state-of-the-art area- and energy-efficiency.
NB-LDPC code achieves better error-correcting performance than LDPC code at the cost of higher decoding complexity. However, the factor graph is simplified, permitting a fully parallel architecture with low wiring overhead. To reduce the dynamic power of the decoder, a fine-grained dynamic clock gating technique is applied based on node-level convergence. This technique greatly reduces dynamic power allowing the decoder to achieve high energy-efficiency while achieving high throughput.
The recently invented polar code has a similar error-correcting performance to LDPC code of comparable block length. However, the easy reconfigurability of code rate as well as block length makes it desirable in numerous applications where LDPC is not competitive. In addition, the regular structure and simple processing enables a highly efficient decoder in terms of area and power. Using the belief propagation algorithm with architectural and memory improvements, a polar decoder is demonstrated achieving high throughput and high energy- and area-efficiency.
The demonstrated energy-efficient decoders have advanced the state-of-the-art. The decoders will allow the continued reduction of decode energy for the latest communication and storage applications. The developed techniques are widely applicable to designing low-power DSP processors.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/108731/1/parkyoun_1.pd
Error Characterization and Correction Techniques for Reliable STT-RAM Designs
The concerns on the continuous scaling of mainstream memory technologies have motivated tremendous investment to emerging memories. Being a promising candidate, spin-transfer torque random access memory (STT-RAM) offers nanosecond access time comparable to SRAM, high integration density close to DRAM, non-volatility as Flash memory, and good scalability. It is well positioned as the replacement of SRAM and DRAM for on-chip cache and main memory applications. However, reliability issue continues being one of the major challenges in STT-RAM memory designs due to the process variations and unique thermal fluctuations, i.e., the stochastic resistance switching property of magnetic devices.
In this dissertation, I decoupled the reliability issues as following three-folds: First, the characterization of STT-RAM operation errors often require expensive Monte-Carlo runs with hybrid magnetic-CMOS simulation steps, making it impracticable for architects and system designs; Second, the state of the art does not have sufficiently understanding on the unique reliability issue of STT-RAM, and conventional error correction codes (ECCs) cannot efficiently handle such errors; Third, while the information density of STT-RAM can be boosted by multi-level cell (MLC) design, the more prominent reliability concerns and the complicated access mechanism greatly limit its applications in memory subsystems.
Thus, I present a novel through solution set to both characterize and tackle the above reliability challenges in STT-RAM designs. In the first part of the dissertation, I introduce a new characterization method that can accurately and efficiently capture the multi-variable design metrics of STT-RAM cells; Second, a novel ECC scheme, namely, content-dependent ECC (CD-ECC), is developed to combat the characterized asymmetric errors of STT-RAM at 0->1 and 1->0 bit flipping's; Third, I present a circuit-architecture design, namely state-restricted multi-level cell (SR-MLC) STT-RAM design, which simultaneously achieves high information density, good storage reliability and fast write speed, making MLC STT-RAM accessible for system designers under current technology node. Finally, I conclude that efficient robust (or ECC) designs for STT-RAM require a deep holistic understanding on three different levels-device, circuit and architecture. Innovative ECC schemes and their architectural applications, still deserve serious research and investigation in the near future