A Survey of Prediction and Classification Techniques in Multicore Processor Systems

In multicore processor systems, being able to accurately predict the future provides new optimization opportunities, which otherwise could not be exploited. For example, an oracle able to predict a certain application\u27s behavior running on a smart phone could direct the power manager to switch to appropriate dynamic voltage and frequency scaling modes that would guarantee minimum levels of desired performance while saving energy consumption and thereby prolonging battery life. Using predictions enables systems to become proactive rather than continue to operate in a reactive manner. This prediction-based proactive approach has become increasingly popular in the design and optimization of integrated circuits and of multicore processor systems. Prediction transforms from simple forecasting to sophisticated machine learning based prediction and classification that learns from existing data, employs data mining, and predicts future behavior. This can be exploited by novel optimization techniques that can span across all layers of the computing stack. In this survey paper, we present a discussion of the most popular techniques on prediction and classification in the general context of computing systems with emphasis on multicore processors. The paper is far from comprehensive, but, it will help the reader interested in employing prediction in optimization of multicore processor systems

Radiation safety based on the sky shine effect in reactor

In the reactor operation, neutrons and gamma rays are the most dominant radiation. As protection, lead and concrete shields are built around the reactor. However, the radiation can penetrate the water shielding inside the reactor pool. This incident leads to the occurrence of sky shine where a physical phenomenon of nuclear radiation sources was transmitted panoramic that extends to the environment. The effect of this phenomenon is caused by the fallout radiation into the surrounding area which causes the radiation dose to increase. High doses of exposure cause a person to have stochastic effects or deterministic effects. Therefore, this study was conducted to measure the radiation dose from sky shine effect that scattered around the reactor at different distances and different height above the reactor platform. In this paper, the analysis of the radiation dose of sky shine effect was measured using the experimental metho

Physical parameter-aware Networks-on-Chip design

PhD ThesisNetworks-on-Chip (NoCs) have been proposed as a scalable, reliable and power-efficient communication fabric for chip multiprocessors (CMPs) and multiprocessor systems-on-chip (MPSoCs). NoCs determine both the performance and the reliability of such systems, with a significant power demand that is expected to increase due to developments in both technology and architecture. In terms of architecture, an important trend in many-core systems architecture is to increase the number of cores on a chip while reducing their individual complexity. This trend increases communication power relative to computation power. Moreover, technology-wise, power-hungry wires are dominating logic as power consumers as technology scales down. For these reasons, the design of future very large scale integration (VLSI) systems is moving from being computation-centric to communication-centric. On the other hand, chip’s physical parameters integrity, especially power and thermal integrity, is crucial for reliable VLSI systems. However, guaranteeing this integrity is becoming increasingly difficult with the higher scale of integration due to increased power density and operating frequencies that result in continuously increasing temperature and voltage drops in the chip. This is a challenge that may prevent further shrinking of devices. Thus, tackling the challenge of power and thermal integrity of future many-core systems at only one level of abstraction, the chip and package design for example, is no longer sufficient to ensure the integrity of physical parameters. New designtime and run-time strategies may need to work together at different levels of abstraction, such as package, application, network, to provide the required physical parameter integrity for these large systems. This necessitates strategies that work at the level of the on-chip network with its rising power budget. This thesis proposes models, techniques and architectures to improve power and thermal integrity of Network-on-Chip (NoC)-based many-core systems. The thesis is composed of two major parts: i) minimization and modelling of power supply variations to improve power integrity; and ii) dynamic thermal adaptation to improve thermal integrity. This thesis makes four major contributions. The first is a computational model of on-chip power supply variations in NoCs. The proposed model embeds a power delivery model, an NoC activity simulator and a power model. The model is verified with SPICE simulation and employed to analyse power supply variations in synthetic and real NoC workloads. Novel observations regarding power supply noise correlation with different traffic patterns and routing algorithms are found. The second is a new application mapping strategy aiming vii to minimize power supply noise in NoCs. This is achieved by defining a new metric, switching activity density, and employing a force-based objective function that results in minimizing switching density. Significant reductions in power supply noise (PSN) are achieved with a low energy penalty. This reduction in PSN also results in a better link timing accuracy. The third contribution is a new dynamic thermal-adaptive routing strategy to effectively diffuse heat from the NoC-based threedimensional (3D) CMPs, using a dynamic programming (DP)-based distributed control architecture. Moreover, a new approach for efficient extension of two-dimensional (2D) partially-adaptive routing algorithms to 3D is presented. This approach improves three-dimensional networkon- chip (3D NoC) routing adaptivity while ensuring deadlock-freeness. Finally, the proposed thermal-adaptive routing is implemented in field-programmable gate array (FPGA), and implementation challenges, for both thermal sensing and the dynamic control architecture are addressed. The proposed routing implementation is evaluated in terms of both functionality and performance. The methodologies and architectures proposed in this thesis open a new direction for improving the power and thermal integrity of future NoC-based 2D and 3D many-core architectures

Eco-efficient process based on conventional machining as an alternative technology to chemical milling of aeronautical metal skin panels

El fresado químico es un proceso diseñado para la reducción de peso de pieles metálicas que, a pesar de los problemas medioambientales asociados, se utiliza en la industria aeronáutica desde los años 50. Entre sus ventajas figuran el cumplimiento de las estrictas tolerancias de diseño de piezas aeroespaciales y que pese a ser un proceso de mecanizado, no induce tensiones residuales. Sin embargo, el fresado químico es una tecnología contaminante y costosa que tiende a ser sustituida. Gracias a los avances realizados en el mecanizado, la tecnología de fresado convencional permite alcanzar las tolerancias requeridas siempre y cuando se consigan evitar las vibraciones y la flexión de la pieza, ambas relacionadas con los parámetros del proceso y con los sistemas de utillaje empleados. Esta tesis analiza las causas de la inestabilidad del corte y la deformación de las piezas a través de una revisión bibliográfica que cubre los modelos analíticos, las técnicas computacionales y las soluciones industriales en estudio actualmente. En ella, se aprecia cómo los modelos analíticos y las soluciones computacionales y de simulación se centran principalmente en la predicción off-line de vibraciones y de posibles flexiones de la pieza. Sin embargo, un enfoque más industrial ha llevado al diseño de sistemas de fijación, utillajes, amortiguadores basados en actuadores, sistemas de rigidez y controles adaptativos apoyados en simulaciones o en la selección estadística de parámetros. Además se han desarrollado distintas soluciones CAM basadas en la aplicación de gemelos virtuales. En la revisión bibliográfica se han encontrado pocos documentos relativos a pieles y suelos delgados por lo que se ha estudiado experimentalmente el efecto de los parámetros de corte en su mecanizado. Este conjunto de experimentos ha demostrado que, pese a usar un sistema que aseguraba la rigidez de la pieza, las pieles se comportaban de forma diferente a un sólido rígido en términos de fuerzas de mecanizado cuando se utilizaban velocidades de corte cercanas a la alta velocidad. También se ha verificado que todas las muestras mecanizadas entraban dentro de tolerancia en cuanto a la rugosidad de la pieza. Paralelamente, se ha comprobado que la correcta selección de parámetros de mecanizado puede reducir las fuerzas de corte y las tolerancias del proceso hasta un 20% y un 40%, respectivamente. Estos datos pueden tener aplicación industrial en la simplificación de los sistemas de amarre o en el incremento de la eficiencia del proceso. Este proceso también puede mejorarse incrementando la vida de la herramienta al utilizar fluidos de corte. Una correcta lubricación puede reducir la temperatura del proceso y las tensiones residuales inducidas a la pieza. Con este objetivo, se han desarrollado diferentes lubricantes, basados en el uso de líquidos iónicos (IL) y se han comparado con el comportamiento tribológico del par de contacto en seco y con una taladrina comercial. Los resultados obtenidos utilizando 1 wt% de los líquidos iónicos en un tribómetro tipo pin-on-disk demuestran que el IL no halogenado reduce significativamente el desgaste y la fricción entre el aluminio, material a mecanizar, y el carburo de tungsteno, material de la herramienta, eliminando casi toda la adhesión del aluminio sobre el pin, lo que puede incrementar considerablemente la vida de la herramienta.Chemical milling is a process designed to reduce the weight of metals skin panels. This process has been used since 1950s in the aerospace industry despite its environmental concern. Among its advantages, chemical milling does not induce residual stress and parts meet the required tolerances. However, this process is a pollutant and costly technology. Thanks to the last advances in conventional milling, machining processes can achieve similar quality results meanwhile vibration and part deflection are avoided. Both problems are usually related to the cutting parameters and the workholding. This thesis analyses the causes of the cutting instability and part deformation through a literature review that covers analytical models, computational techniques and industrial solutions. Analytics and computational solutions are mainly focused on chatter and deflection prediction and industrial approaches are focused on the design of workholdings, fixtures, damping actuators, stiffening devices, adaptive control systems based on simulations and the statistical parameters selection, and CAM solutions combined with the use of virtual twins applications. In this literature review, few research works about thin-plates and thin-floors is found so the effect of the cutting parameters is also studied experimentally. These experiments confirm that even using rigid workholdings, the behavior of the part is different to a rigid body at high speed machining. On the one hand, roughness values meet the required tolerances under every set of the tested parameters. On the other hand, a proper parameter selection reduces the cutting forces and process tolerances by up to 20% and 40%, respectively. This fact can be industrially used to simplify workholding and increase the machine efficiency. Another way to improve the process efficiency is to increase tool life by using cutting fluids. Their use can also decrease the temperature of the process and the induced stresses. For this purpose, different water-based lubricants containing three types of Ionic Liquids (IL) are compared to dry and commercial cutting fluid conditions by studying their tribological behavior. Pin on disk tests prove that just 1wt% of one of the halogen-free ILs significantly reduces wear and friction between both materials, aluminum and tungsten carbide. In fact, no wear scar is noticed on the ball when one of the ILs is used, which, therefore, could considerably increase tool life

Embedded dynamic programming networks for networks-on-chip

PhD ThesisRelentless technology downscaling and recent technological advancements in three dimensional integrated circuit (3D-IC) provide a promising prospect to realize heterogeneous system-on-chip (SoC) and homogeneous chip multiprocessor (CMP) based on the networks-onchip (NoCs) paradigm with augmented scalability, modularity and performance. In many cases in such systems, scheduling and managing communication resources are the major design and implementation challenges instead of the computing resources. Past research efforts were mainly focused on complex design-time or simple heuristic run-time approaches to deal with the on-chip network resource management with only local or partial information about the network. This could yield poor communication resource utilizations and amortize the benefits of the emerging technologies and design methods. Thus, the provision for efficient run-time resource management in large-scale on-chip systems becomes critical. This thesis proposes a design methodology for a novel run-time resource management infrastructure that can be realized efficiently using a distributed architecture, which closely couples with the distributed NoC infrastructure. The proposed infrastructure exploits the global information and status of the network to optimize and manage the on-chip communication resources at run-time. There are four major contributions in this thesis. First, it presents a novel deadlock detection method that utilizes run-time transitive closure (TC) computation to discover the existence of deadlock-equivalence sets, which imply loops of requests in NoCs. This detection scheme, TC-network, guarantees the discovery of all true-deadlocks without false alarms in contrast to state-of-the-art approximation and heuristic approaches. Second, it investigates the advantages of implementing future on-chip systems using three dimensional (3D) integration and presents the design, fabrication and testing results of a TC-network implemented in a fully stacked three-layer 3D architecture using a through-silicon via (TSV) complementary metal-oxide semiconductor (CMOS) technology. Testing results demonstrate the effectiveness of such a TC-network for deadlock detection with minimal computational delay in a large-scale network. Third, it introduces an adaptive strategy to effectively diffuse heat throughout the three dimensional network-on-chip (3D-NoC) geometry. This strategy employs a dynamic programming technique to select and optimize the direction of data manoeuvre in NoC. It leads to a tool, which is based on the accurate HotSpot thermal model and SystemC cycle accurate model, to simulate the thermal system and evaluate the proposed approach. Fourth, it presents a new dynamic programming-based run-time thermal management (DPRTM) system, including reactive and proactive schemes, to effectively diffuse heat throughout NoC-based CMPs by routing packets through the coolest paths, when the temperature does not exceed chip’s thermal limit. When the thermal limit is exceeded, throttling is employed to mitigate heat in the chip and DPRTM changes its course to avoid throttled paths and to minimize the impact of throttling on chip performance. This thesis enables a new avenue to explore a novel run-time resource management infrastructure for NoCs, in which new methodologies and concepts are proposed to enhance the on-chip networks for future large-scale 3D integration.Iraqi Ministry of Higher Education and Scientific Research (MOHESR)

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast

A survey on scheduling and mapping techniques in 3D Network-on-chip

Network-on-Chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores and allow those cores to achieve higher performance by outsourcing their communication tasks. Mapping and Scheduling methodologies are key elements in assigning application tasks, allocating the tasks to the IPs, and organising communication among them to achieve some specified objectives. The goal of this paper is to present a detailed state-of-the-art of research in the field of mapping and scheduling of applications on 3D NoC, classifying the works based on several dimensions and giving some potential research directions