2,872 research outputs found
Separately, Connectedly: Exploring Trauma Through Ekphrasis in Contemporary Novels
This thesis examines ekphrasis as a rhetorical tool to explore, represent, and contemplate trauma affect in contemporary novels. From the Greek phrase for ‘description,’ ekphrasis is part of a long and ancient literary tradition, dating as far back as the ancient depictions of art on urns, weaponry, as well as more disambiguated descriptions of scenes and people. The uses of ekphrasis as a literary device are broad and complex, but its use is under-researched in contemporary novels, and there is a near total absence of investigation into ekphrasis within the novel as a means of contemplating and understanding the affect of a condition that is inherently abstract and disorienting.Literary trauma theory has evolved considerably in recent years. In keeping with important findings in psychology and psychiatric research, there is a broad recognition that rethinking trauma representation beyond the recitation and reliving of events and into textured descriptions of trauma affect is essential for thoughtful, nuanced explorations of an experience that resists narrative convenience. As a result, there are increased calls to accept and represent its inherent fractured nature and resist the authorial temptation to forge a story around it that fits neatly into a cohesive whole. This thesis proposes a framework for considering how various aspects of ekphrastic descriptions of real and imagined art as well as their connotative and denotative significance in the novel reveals nuance in the representation of trauma affect through the activation of language and image. The contemporary novels explored herein are: The Goldfinch by Donna Tartt, What I Loved by Siri Hustvedt, and How to Be Both by Ali Smith. Each of these novels present ekphrasis and affect differently, which enables broader testing of the flexibility of the proposed framework
ACiS: smart switches with application-level acceleration
Network performance has contributed fundamentally to the growth of supercomputing over the past decades. In parallel, High Performance Computing (HPC) peak performance has depended, first, on ever faster/denser CPUs, and then, just on increasing density alone. As operating frequency, and now feature size, have levelled off, two new approaches are becoming central to achieving higher net performance: configurability and integration. Configurability enables hardware to map to the application, as well as vice versa. Integration enables system components that have generally been single function-e.g., a network to transport data—to have additional functionality, e.g., also to operate on that data. More generally, integration enables compute-everywhere: not just in CPU and accelerator, but also in network and, more specifically, the communication switches.
In this thesis, we propose four novel methods of enhancing HPC performance through Advanced Computing in the Switch (ACiS). More specifically, we propose various flexible and application-aware accelerators that can be embedded into or attached to existing communication switches to improve the performance and scalability of HPC and Machine Learning (ML) applications. We follow a modular design discipline through introducing composable plugins to successively add ACiS capabilities.
In the first work, we propose an inline accelerator to communication switches for user-definable collective operations. MPI collective operations can often be performance killers in HPC applications; we seek to solve this bottleneck by offloading them to reconfigurable hardware within the switch itself. We also introduce a novel mechanism that enables the hardware to support MPI communicators of arbitrary shape and that is scalable to very large systems.
In the second work, we propose a look-aside accelerator for communication switches that is capable of processing packets at line-rate. Functions requiring loops and states are addressed in this method. The proposed in-switch accelerator is based on a RISC-V compatible Coarse Grained Reconfigurable Arrays (CGRAs).
To facilitate usability, we have developed a framework to compile user-provided C/C++ codes to appropriate back-end instructions for configuring the accelerator.
In the third work, we extend ACiS to support fused collectives and the combining of collectives with map operations. We observe that there is an opportunity of fusing communication (collectives) with computation. Since the computation can vary for different applications, ACiS support should be programmable in this method.
In the fourth work, we propose that switches with ACiS support can control and manage the execution of applications, i.e., that the switch be an active device with decision-making capabilities. Switches have a central view of the network; they can collect telemetry information and monitor application behavior and then use this information for control, decision-making, and coordination of nodes.
We evaluate the feasibility of ACiS through extensive RTL-based simulation as well as deployment in an open-access cloud infrastructure. Using this simulation framework, when considering a Graph Convolutional Network (GCN) application as a case study, a speedup of on average 3.4x across five real-world datasets is achieved on 24 nodes compared to a CPU cluster without ACiS capabilities
Design and characterisation of monolithic CMOS detectors for high energy particle physics and SEU radiation tests for ATLAS Inner Tracker Upgrade readout chip
This thesis covers the characterisation results and the design of monolithic CMOS detectors designed in TowerJazz 180nm CMOS technology for High Energy Particle Physics applications. Three different detectors have been studied the MALTA, the Mini-MALTA and the MALTA2. The MALTA sensor showed some efficiency losses at the corners of the pixels after irradiation, which meant that it was not suitable for the radiation environments in which it was supposed to be installed. Therefore, the front-end electronics and the fabrication process were modified to overcome this issue. The Mini-MALTA prototype was designed including the above mentioned improvements, fabricated and fully characterised. Finally taking into account all the knowledge acquired during these years of developments another large scale sensor the MALTA2 has been produced which should be radiation tolerant and have very good time resolution. The description and studies of the different architectures used in this family of detectors are covered and a simulation to estimate the bandwidth capabilities have been reported.
Furthermore, this work will present characterisation of single event effects in the ITkPixV1, the prototype version of the ATLAS Inner Tracker Upgrade chip for the High Luminosity LHC. Measurements were made in testbeam campaigns with high energy ions and protons to evaluate the level of single event effects in the chip
A SciFi tracker for the LHCb experiment
The quest to understand the prevalence of matter over antimatter in the observable universe drives the Large Hadron Collider Beauty (LHCb) Experiment at CERN, situated beneath the France-Switzerland border. This thesis focuses on a detector upgrade crucial to enhance the sensitivity of the LHCb Experiment. A key ingredient of this upgrade is the Scintillating Fiber Detector (SciFi) Tracker.The introduction of the SciFi replaced key components like the Outer and Inner Tracker, improving tracking efficiency and spatial resolution.To ensure SciFi's radiation resilience, comprehensive tests were conducted, that revealed effects on Field-Programmable Gate Arrays (FPGAs), including speed degradation, leakage current, re-programmability loss, Single Event Upsets (SEU), and Single Event Latch-ups (SEL).Results indicated that speed degradation, leakage current, and SELs were manageable during the detector's lifetime. However, FPGAs became unprogrammable after a certain radiation exposure, necessitating operational planning. Mitigation strategies, like triple modular redundancy, reduced SEUs to an acceptable level.Mass-produced SciFi modules and readout electronics underwent their first particle beam test, allowing optimization of operating parameters of the front-end electronics, such as clustering coefficients, thresholds, and shaper settings.Resolution analysis demonstrated compliance with detector specifications. With an efficiency surpassing 99\% and a spatial resolution better than 70 µm, SciFi is validated for LHCb operation.As SciFi is commissioned, the configurations explored in this thesis offer valuable insights for optimizing the detector during commissioning and beyond
Rapid Prototyping and Functional Verification of Power Efficient AI Processor on FPGA
Prototyping a design on a Field Programmable Gate Array (FPGA) involves different stages such as developing a design, performing synthesis, handling placement and routing and finally generating the programming bit file for the FPGA. After successful completion of the above stages, it is important to functionally verify the design. This thesis addresses the challenges involved in rapid prototyping and functional verification of a low power AI processor provided by the industry partner. This research also addresses the methodology used in generating programming bit file and testing the design. Traditional method of testing a design using RTL level testbench utilises more time and relies on functioning of other components associated with the design. This thesis incorporated a new technique of testing the design using software programs focusing on verification of the functionality of a particular module without depending on the other. This methodology reduced the time for functionality verification for part of the design from approximately 1 month to about 2 weeks. Finally, using the methodology mentioned above, the design was synthesized for two FPGA kits, along with analysing the power consumption of the design. The results show the low power nature of the design as it does not use any external memory resulting in faster Arithmetic Logic Unit (ALU) operations thereby saving time to access the data
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