ABSTRACT: An explicit pulsed dual edge triggered sense amplifier flip flops (DET-FF).In this dual edge triggered sense amplifier flip flop is used for low-power consumption and high performance application. By incorporating the dual edge triggering mechanism, the dual edge triggered flip flop is able to achieve low power consumption that has minimum delay. Clock gating is a popular technique used in many synchronous circuits; hence, the power dissipation is very much reduced. Reducing dynamic power reduction. Clock gating saves power by adding more logic gates in the circuit. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. KEYWORDS: Clock pulse gating,high performance,low power,delay,pulse dual edge triggered, sense amplifier flip flop. I. INTRODUCTION In many digital very large scale integration (VLSI) design, which consists of the clock distribution network and timing elements, is one of the most power consumption. Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the whole synchronous circuit. In this dual edge triggered sense amplifier as developed from single edge triggered sense amplifier flip flops. At each rising or falling edge of a clock signal, the data stored in a set of flip-flops is readily available so that it can be applied as inputs to other combinational or sequential circuitry. Such flip-flops that store data on both the leading edge and the trailing edge of a clock pulse are referred to as double-edge triggered flip-flops otherwise it is called as single edge triggered flip-flops. The dual edge triggering is a very important technique is to reduce the power consumption in the clock distribution network. In this dual edge triggering is to introduce the clock gating. In this clock gating with clock storage element is to reduce the dynamic power. Two types of clock gating are used in the dual edge triggering mechanism. These are latch free clock gating and latch based clock gating. When technology scales down, total power dissipation will decrease and at the same time delay varies depends upon supply voltage, threshold voltage, oxide thickness. II.DUAL EDGE TRIGGERED FLIP FLOP The dual edge triggered flip flops have two stages. These are pulse generator stage and latching stage. If the clock pulse as the input of the pulse generator. It produces the triggering pulse signal. Latching stage as generate the output pulse signal. In this dual edge triggering flip flop used two types of clock gating. These are latch based clock gating and latch free clock gating. The general block is shown i
