A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

DOHERTY AMPLIFIER LINEARIZATION BY DIGITAL INJECTION METHODS

Verification of two linearization methods, applied on asymmetrical two-way microstrip Doherty amplifier in experiment and on symmetrical two-way Doherty amplifier in simulation, is performed in this paper. The laboratory set-ups are formed to generate the baseband nonlinear linearization signals of the second-order. After being tuned in magnitude and phase in the digital domain the linearization signals modulate the second harmonics of fundamental carrier. In the first method, adequately processed signals are then inserted at the input and output of the main Doherty amplifier transistor, whereas in the second method, they are injected at the outputs of the Doherty main and auxiliary amplifier transistors. The experimental results are obtained for 64QAM digitally modulated signals. As a proof of concept, the linearization methods are also verified in simulation, for Doherty amplifier designed to work in 5G band below 6 GHz, utilizing 20 MHz LTE signal

3-Way Doherty Power Amplifiers: Design Guidelines and MMIC Implementation at 28 GHz

This article presents the design strategy and the implementation of a three-way Doherty power amplifier (DPA3W) to enhance the efficiency at deep power back-off. Theoretical design equations are derived, based on which design charts are drawn to explore the available design space, accounting for practical constraints related to the available technology and selected application. The proposed design strategy is demonstrated by the design, fabrication and experimental characterization of a three-way multistage Doherty amplifier optimized for efficiency peaks at 6 and 12 dB back-off. The amplifier is realized on the WIN Semiconductors 150 nm GaN-SiC high-electron-mobility transistor (HEMT) monolithic process at 28 GHz, targeting 5G applications. The prototype achieves saturated output power in excess of 34 dBm and power added efficiency of the order of 15% from 6 to 12 dB back-off, demonstrating competitive performance and a good agreement between simulations and measurements, thus validating the approach

A 39-GHz Doherty-Like Power Amplifier with 22-dBm Output Power and 21% Power-Added Efficiency at 6-dB Power Back-Off

© 2024, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This is the accepted manuscript version of a conference paper which has been published in final form at https://doi.org/10.1109/JETCAS.2024.3351075The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical loadmodulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use of a non-50 Ω load at the isolation port of the output quadrature coupler. Moreover, magnitude and phase control networks are carefully designed to generate the specific magnitude and phase information for the designed S-LMBA. To demonstrate the proposed ideas, the SLMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power (Psat) with a maximum poweradded efficiency (PAE) of 25.7% is achieved. In addition, 1.68 times drain efficiency enhancement is obtained over an ideal Class-B operation, when the designed S-LMBA is operated at 6 dB power back-off. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude (EVMrms) above -22.5 dB and adjacent channel power ratio (ACPR) of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadratureamplitude- modulation (QAM) signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.Peer reviewe

Efficient and Wideband Load Modulated Power Amplifiers for Wireless Communication

The increasing demand for mobile data traffic has resulted in new challenges and requirements for the development of the wireless communication infrastructure. With the transition to higher frequencies and multi-antenna systems, radio frequency (RF) hardware performance, especially the power amplifier (PA), becomes increasingly important. Enhancing PA energy efficiency and bandwidth is vital for maximizing channel capacity, reducing operational costs, and facilitating integration.In the first part of the thesis, the bandwidth limitations of the standard two-way Doherty PA are discussed. A comprehensive analysis is provided, and the frequency responses of different Doherty combiner networks are presented. Furthermore, a Doherty combiner network is proposed, notable for its inherent broadband frequency and its capacity to account for the influence of output parasitics and packaged components from the active devices. The introduced Doherty combiner network is experimentally verified by a wideband gallium nitride (GaN) Doherty PA operating over 1.6-2.7 GHz.In the second part of the thesis, an analytically based combiner synthesis approach for the three-stage Doherty PA is proposed and presented. A compact output combiner network, together with the input phase delays, is derived directly from transistor load-pull data and the PA design requirements. The technique opens up new design space for three-stage Doherty PAs with reconfigurable high-efficiency power back-off levels. The utility of the proposed technique is demonstrated by the implementation of a 30-W GaN three-stage Doherty PA prototype at 2.14 GHz. Measurements show that a drain efficiency of 68% and 55% is exhibited at 6- and 10-dB back-off power, respectively.In the third part, a new PA architecture named the circulator load modulated amplifier (CLMA), is proposed. This architecture utilizes active load modulation for achieving enhanced back-off efficiency. Two active devices are incorporated in this innovative architecture, and a non-reciprocal circulator-based combiner is leveraged. Following this, the sequential CLMA (SCLMA) is introduced, characterized by its ability to enhance back-off efficiency without the necessity of load modulation. GaN demonstrator circuits for both CLMA and SCLMA architectures, whether with dual-input or RF single-input, are designed and fabricated, with excellent performance being measured.\ua0The thesis contributes novel design techniques and architectures to enhance PA efficiency and bandwidth. These findings pave the way for energy-efficient and adaptable RF transmitters in future wireless communication systems

A 40-GHz Load Modulated Balanced Power Amplifier using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS

© 2023 IEEE - All rights reserved. This is the accepted manuscript version of an article which has been published in final form at https://doi.org/10.1109/TCSI.2023.3282731 ​​​​​​​In this work, a ten-way power-combined poweramplifier is designed using a load modulated balanced amplifier(LMBA)-based architecture. To provide the required magnitudeand phase controls between the main and control-signal paths ofthe LMBA, an unequal power splitter and a phase compensationnetwork are proposed. As proof of concept, the designed poweramplifier is implemented in a 45-nm SOI CMOS process. At 40GHz, it delivers a 25.1 dBm Psat with a peak power-addedefficiency (PAE) of 27.9%. At 6-dB power back-off level, itachieves 1.39 times drain efficiency enhancement over an idealClass-B power amplifier. Using a 200-MHz single-carrier 64-QAMsignal, the designed amplifier delivers an average output power of16.5 dBm with a PAE of 13.1% at an EVMrms of -23.9 dB andACPR of -25.3 dBc. The die size, including all testing pads, is only1.92 mm2. To the best of the authors’ knowledge, compared withthe other recently published silicon-based LMBAs, this designachieves the highest Psat.Peer reviewe

A 5-W GaN Doherty Amplifier for Ka-Band Satellite Downlink With 4-GHz Bandwidth and 17-dB NPR

This letter presents the design and experimental characterization of a GaN-Si monolithic Doherty power amplifier (PA) for the Ka-band satellite downlink. The fabricated amplifier favorably compares with the current state of the art, achieving from 16.3 to 20.3 GHz (4 GHz, 22% relative bandwidth), a record band to date, 36.6-37.7-dBm output power, 23%-31% power-added efficiency, 18-22-dB gain at saturation, and around 20% power-added efficiency at 6-dB output back-off. At 18.8 GHz, the amplifier shows a noise-to-power ratio higher than 17 dB at all power levels, making it suitable for satellite applications where additional linearization is usually unfeasible