Foundry-Enabled Scalable All-to-All Optical Interconnects Using Silicon Nitride Arrayed Waveguide Router Interposers and Silicon Photonic Transceivers

This paper summarizes our latest results of integrated all-to-all optical interconnect systems using compact, low-loss silicon nitride (SiN) arrayed waveguide grating router (AWGR) through AIM photonics' multiple-project-wafer services. In particular, we have designed, taped out, and initially characterized a chip-scale silicon photonic low-latency interconnect optical network switch (Si-LIONS) system with an 8 × 8 200 GHz spacing cyclic SiN AWGR, 64 microdisk modulators, and 64 on-chip germanium photodector (PD). The 8 × 8 SiN AWGR in design has a measured insertion loss of 1.8 dB and a crosstalk of -13 dB, with a footprint of 1.3 mm × 0.9 mm. We measured an error-free performance of the microdisk modulator at 10 Gb/s upon 1Vpp voltage swing. We demonstrated wavelength routing with error-free data transmission using the on-chip modulator, SiN AWGR, and an external PD. We have designed and taped out the optical interposer version of the all-to-all system using SiN waveguides and low-loss chip-to-interposer couplers. Finally, we illustrate our preliminary designs and results of 16 × 16 and 32 × 32 SiN AWGRs, and discuss the possibility of scaling beyond 1024 × 1024 all-to-all interconnections with reduced number of wavelengths (e.g., 64) using the Thin-CLOS architecture

Multi-level optical signal generation using a segmented-electrode InP IQ-MZM with integrated CMOS binary drivers

We present a segmented-electrode InP IQ-MZM, capable of multi-level optical signal generation (5-bit per I/Q arm) by employing direct digital drive from integrated, low-power (1W) CMOS binary drivers. Programmable, multi-level operation is demonstrated experimentally on one MZM of the device

Collective Communication Patterns Using Time-Reversal Terahertz Links at the Chip Scale

Wireless communications in the terahertz band have been recently proposed as complement to conventional wired interconnects within computing packages. Such environments are typically highly reverberant, hence showing long channel impulse responses and severely limiting the achievable rates. Fortunately, this communications scenario is static and can be pre-characterized, which opens the door to techniques such as time reversal. Time reversal acts a spatial matched filter and has a spatiotemporal focusing effect, which allows not only to increase the achievable symbol rates, but also to create multiple spatial channels. In this paper, the multi-user capability of time reversal is explored in the context of wireless communications in the terahertz band within a computing package. Full-wave simulations are carried out to validate the approach, whereas modulation streams are simulated to evaluate the error rate as a function of the transmitted power, symbol rate, and number of simultaneous transmissions

Advancement of photonic integration technology for space applications: A x-band scan-on-receive synthetic aperture radar receiver with electro-photonic beamforming and frequency downconversion capability

Synthetic Aperture Radar is a well-known technique for remote sensing applications with great advantages like uninterrupted imaging capabilities even at night or in presence of cloud cover. However, spaceborne SAR sensors face major challenges such as cost and size, which are among the barriers against their applicability for future constellations of low-Earth observation applications. SAR sensors are not compact and require large or medium-sized satellites, which cost hundreds million dollars. To solve these challenges, the recently started SPACEBEAM project, funded by the European Commission, aims at developing a novel SAR Scan-on-Receive approach, exploiting a hybrid integrated optical beamforming network (iOBFN). The compactness and frequency flexibility of the proposed photonic solution complies with the requirements of future constellations of low-Earth orbit satellites in terms of size, weight, power consumption, and cost (SWaP-C). In the design of the SCORE SAR receiver module, we target the development of an X-band receiver having a large swath width of 50 km (5 times wider than state-of-art spaceborne SAR systems), although at the same time enabling a fine spatial resolution of 1.5 m in both along-track and across-track directions. In this paper, we present specifications and preliminary design of the SCORE-SAR receiver at equipment level, where we aim at the realization of a hermetically packaged hybrid InP/TriPleX™ photonic integrated circuit (PIC) for this application. We target the design for the PIC as well as for the RF front-end and control electronics, enabling the electro-photonic frequency down-conversion of the RF signals and the fast control of iOBFN with <300 ns switching time

Architecting a One-to-many Traffic-Aware and Secure Millimeter-Wave Wireless Network-in-Package Interconnect for Multichip Systems

With the aggressive scaling of device geometries, the yield of complex Multi Core Single Chip(MCSC) systems with many cores will decrease due to the higher probability of manufacturing defects especially, in dies with a large area. Disintegration of large System-on-Chips(SoCs) into smaller chips called chiplets has shown to improve the yield and cost of complex systems. Therefore, platform-based computing modules such as embedded systems and micro-servers have already adopted Multi Core Multi Chip (MCMC) architectures overMCSC architectures. Due to the scaling of memory intensive parallel applications in such systems, data is more likely to be shared among various cores residing in different chips resulting in a significant increase in chip-to-chip traffic, especially one-to-many traffic. This one-to-many traffic is originated mainly to maintain cache-coherence between many cores residing in multiple chips. Besides, one-to-many traffics are also exploited by many parallel programming models, system-level synchronization mechanisms, and control signals. How-ever, state-of-the-art Network-on-Chip (NoC)-based wired interconnection architectures do not provide enough support as they handle such one-to-many traffic as multiple unicast trafficusing a multi-hop MCMC communication fabric. As a result, even a small portion of such one-to-many traffic can significantly reduce system performance as traditional NoC-basedinterconnect cannot mask the high latency and energy consumption caused by chip-to-chipwired I/Os. Moreover, with the increase in memory intensive applications and scaling of MCMC systems, traditional NoC-based wired interconnects fail to provide a scalable inter-connection solution required to support the increased cache-coherence and synchronization generated one-to-many traffic in future MCMC-based High-Performance Computing (HPC) nodes. Therefore, these computation and memory intensive MCMC systems need an energy-efficient, low latency, and scalable one-to-many (broadcast/multicast) traffic-aware interconnection infrastructure to ensure high-performance. Research in recent years has shown that Wireless Network-in-Package (WiNiP) architectures with CMOS compatible Millimeter-Wave (mm-wave) transceivers can provide a scalable, low latency, and energy-efficient interconnect solution for on and off-chip communication. In this dissertation, a one-to-many traffic-aware WiNiP interconnection architecture with a starvation-free hybrid Medium Access Control (MAC), an asymmetric topology, and a novel flow control has been proposed. The different components of the proposed architecture are individually one-to-many traffic-aware and as a system, they collaborate with each other to provide required support for one-to-many traffic communication in a MCMC environment. It has been shown that such interconnection architecture can reduce energy consumption and average packet latency by 46.96% and 47.08% respectively for MCMC systems. Despite providing performance enhancements, wireless channel, being an unguided medium, is vulnerable to various security attacks such as jamming induced Denial-of-Service (DoS), eavesdropping, and spoofing. Further, to minimize the time-to-market and design costs, modern SoCs often use Third Party IPs (3PIPs) from untrusted organizations. An adversary either at the foundry or at the 3PIP design house can introduce a malicious circuitry, to jeopardize an SoC. Such malicious circuitry is known as a Hardware Trojan (HT). An HTplanted in the WiNiP from a vulnerable design or manufacturing process can compromise a Wireless Interface (WI) to enable illegitimate transmission through the infected WI resulting in a potential DoS attack for other WIs in the MCMC system. Moreover, HTs can be used for various other malicious purposes, including battery exhaustion, functionality subversion, and information leakage. This information when leaked to a malicious external attackercan reveals important information regarding the application suites running on the system, thereby compromising the user profile. To address persistent jamming-based DoS attack in WiNiP, in this dissertation, a secure WiNiP interconnection architecture for MCMC systems has been proposed that re-uses the one-to-many traffic-aware MAC and existing Design for Testability (DFT) hardware along with Machine Learning (ML) approach. Furthermore, a novel Simulated Annealing (SA)-based routing obfuscation mechanism was also proposed toprotect against an HT-assisted novel traffic analysis attack. Simulation results show that,the ML classifiers can achieve an accuracy of 99.87% for DoS attack detection while SA-basedrouting obfuscation could reduce application detection accuracy to only 15% for HT-assistedtraffic analysis attack and hence, secure the WiNiP fabric from age-old and emerging attacks

Photonic packaging: transforming silicon photonic integrated circuits into photonic devices

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved

Segmented optical transmitter comprising a CMOS driver array and an InP IQ-MZM for advanced modulation formats

Segmented Mach-Zehnder modulators are promising solutions to generate complex modulation schemes in the migration towards optical links with a higher-spectral efficiency. We present an optical transmitter comprising a segmented-electrode InP IQ-MZM, capable of multilevel optical signal generation (5-bit per I/Q arm) by employing direct digital drive from integrated, low-power (1W) CMOS binary drivers. We discuss the advantages and design tradeoffs of the segmented driver structure and the implementation in a 40 nm CMOS technology. Multilevel operation with combined phase and amplitude modulation is demonstrated experimentally on a single MZM of the device for 2-ASK-2PSK and 4-ASK-2-PSK, showing potential for respectively 16-QAM and 64-QAM modulation in future assemblies

Optical terabit transmitter and receiver based on passive polymer and InP technology for high-speed optical connectivity between datacenters

We demonstrate the hybrid integration of a multi-format tunable transmitter and a coherent optical receiver based on optical polymers and InP electronics and photonics for next generation metro and core optical networks. The transmitter comprises an array of two InP Mach-Zehnder modulators (MZMs) with 42 GHz bandwidth and two passive PolyBoards at the back- and front-end of the device. The back-end PolyBoard integrates an InP gain chip, a Bragg grating and a phase section on the polymer substrate capable of 22 nm wavelength tunability inside the C-band and optical waveguides that guide the light to the inputs of the two InP MZMs. The front-end PolyBoard provides the optical waveguides for combing the In-phase and Quadrature-phase modulated signals via an integrated thermo-optic phase shifter for applying the pi/2 phase-shift at the lower arm and a 3-dB optical coupler at the output. Two InP-double heterojunction bipolar transistor (InP-DHBT) 3-bit power digital-to-analog converters (DACs) are hybridly integrated at either side of the MZM array chip in order to drive the IQ transmitter with QPSK, 16-QAM and 64-QAM encoded signals. The coherent receiver is based on the other side on a PolyBoard, which integrates an InP gain chip and a monolithic Bragg grating for the formation of the local oscillator laser, and a monolithic 90° optical hybrid. This PolyBoard is further integrated with a 4-fold InP photodiode array chip with more than 80 GHz bandwidth and two high-speed InP-DHBT transimpedance amplifiers (TIAs) with automatic gain control. The transmitter and the receiver have been experimentally evaluated at 25Gbaud over 100 km for mQAM modulation showing bit-error-rate (BER) performance performance below FEC limit

High Performance Silicon Photonic Interconnected Systems

Advances in data-driven applications, particularly artificial intelligence and deep learning, are driving the explosive growth of computation and communication in today’s data centers and high-performance computing (HPC) systems. Increasingly, system performance is not constrained by the compute speed at individual nodes, but by the data movement between them. This calls for innovative architectures, smart connectivity, and extreme bandwidth densities in interconnect designs. Silicon photonics technology leverages mature complementary metal-oxide-semiconductor (CMOS) manufacturing infrastructure and is promising for low cost, high-bandwidth, and reconfigurable interconnects. Flexible and high-performance photonic switched architectures are capable of improving the system performance. The work in this dissertation explores various photonic interconnected systems and the associated optical switching functionalities, hardware platforms, and novel architectures. It demonstrates the capabilities of silicon photonics to enable efficient deep learning training. We first present field programmable gate array (FPGA) based open-loop and closed-loop control for optical spectral-and-spatial switching of silicon photonic cascaded micro-ring resonator (MRR) switches. Our control achieves wavelength locking at the user-defined resonance of the MRR for optical unicast, multicast, and multiwavelength-select functionalities. Digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) are necessary for the control of the switch. We experimentally demonstrate the optical switching functionalities using an FPGA-based switch controller through both traditional multi-bit DAC/ADC and novel single-wired DAC/ADC circuits. For system-level integration, interfaces to the switch controller in a network control plane are developed. The successful control and the switching functionalitiesachieved are essential for system-level architectural innovations as presented in the following sections. Next, this thesis presents two novel photonic switched architectures using the MRR-based switches. First, a photonic switched memory system architecture was designed to address memory challenges in deep learning. The reconfigurable photonic interconnects provide scalable solutions and enable efficient use of disaggregated memory resources for deep learning training. An experimental testbed was built with a processing system and two remote memory nodes using silicon photonic switch fabrics and system performance improvements were demonstrated. The collective results and existing high-bandwidth optical I/Os show the potential of integrating the photonic switched memory to state-of-the-art processing systems. Second, the scaling trends of deep learning models and distributed training workloads are challenging network capacities in today’s data centers and HPCs. A system architecture that leverages SiP switch-enabled server regrouping is proposed to tackle the challenges and accelerate distributed deep learning training. An experimental testbed with a SiP switch-enabled reconfigurable fat tree topology was built to evaluate the network performance of distributed ring all-reduce and parameter server workloads. We also present system-scale simulations. Server regrouping and bandwidth steering were performed on a large-scale tapered fat tree with 1024 compute nodes to show the benefits of using photonic switched architectures in systems at scale. Finally, this dissertation explores high-bandwidth photonic interconnect designs for disaggregated systems. We first introduce and discuss two disaggregated architectures leveraging extreme high bandwidth interconnects with optically interconnected computing resources. We present the concept of rack-scale graphics processing unit (GPU) disaggregation with optical circuit switches and electrical aggregator switches. The architecture can leverage the flexibility of high bandwidth optical switches to increase hardware utilization and reduce application runtimes. A testbed was built to demonstrate resource disaggregation and defragmentation. In addition, we also present an extreme high-bandwidth optical interconnect accelerated low-latency communication architecture for deep learning training. The disaggregated architecture utilizes comb laser sources and MRR-based cross-bar switching fabrics to enable an all-to-all high bandwidth communication with a constant latency cost for distributed deep learning training. We discuss emerging technologies in the silicon photonics platform, including light source, transceivers, and switch architectures, to accommodate extreme high bandwidth requirements in HPC and data center environments. A prototype hardware innovation - Optical Network Interface Cards (comprised of FPGA, photonic integrated circuits (PIC), electronic integrated circuits (EIC), interposer, and high-speed printed circuit board (PCB)) is presented to show the path toward fast lanes for expedited execution at 10 terabits. Taken together, the work in this dissertation demonstrates the capabilities of high-bandwidth silicon photonic interconnects and innovative architectural designs to accelerate deep learning training in optically connected data center and HPC systems