723 research outputs found
Design and Experiment of PZT Network-based Structural Health Monitoring Scanning System
AbstractThe active Lamb wave and piezoelectric transducer (PZT)-based structural health monitoring (SHM) technology is a kind of efficient approach to estimate the health state of aircraft structure. In practical applications, PZT networks are needed to monitor large scale structures. Scanning many of the different PZT actuator-sensor channels within these PZT networks to achieve on-line SHM task is important. Based on a peripheral component interconnect extensions for instrumentation (PXI) platform, an active Lamb wave and PZT network-based integrated multi-channel scanning system (PXI-ISS) is developed for the purpose of practical applications of SHM, which is compact and portable, and can scan large numbers of actuator-sensor channels and perform damage assessing automatically. A PXI-based 4 channels gain-programmable charge amplifier, an external scanning module with 276 actuator-sensor channels and integrated SHM software are proposed and discussed in detail. The experimental research on a carbon fiber composite wing box of an unmanned aerial vehicle (UAV) for verifying the functions of the PXI-ISS is mainly discussed, including the design of PZTs layer, the method of excitation frequency selection, functional test of damage imaging, stability test of the PXI-ISS, and the loading effect on signals. The experimental results have verified the stability and damage functions of this system
Optoelectronic devices and packaging for information photonics
This thesis studies optoelectronic devices and the integration of these components onto
optoelectronic multi chip modules (OE-MCMs) using a combination of packaging
techniques. For this project, (1Ă12) array photodetectors were developed using PIN
diodes with a GaAs/AlGaAs strained layer structure. The devices had a pitch of 250ÎŒm,
operated at a wavelength of 850nm. Optical characterisation experiments of two types
of detector arrays (shoe and ring) were successfully performed. Overall, the shoe
devices achieved more consistent results in comparison with ring diodes, i.e. lower dark
current and series resistance values. A decision was made to choose the shoe design for
implementation into the high speed systems demonstrator. The (1x12) VCSEL array
devices were the optical sources used in my research. This was an identical array at
250ÎŒm pitch configuration used in order to match the photodetector array. These
devices had a wavelength of 850nm. Optoelectronic testing of the VCSEL was
successfully conducted, which provided good beam profile analysis and I-V-P
measurements of the VCSEL array. This was then implemented into a simple
demonstrator system, where eye diagrams examined the systems performance and
characteristics of the full system and showed positive results.
An explanation was given of the following optoelectronic bonding techniques: Wire
bonding and flip chip bonding with its associated technologies, i.e. Solder, gold stud
bump and ACF. Also, technologies, such as ultrasonic flip chip bonding and gold
micro-post technology were looked into and discussed. Experimental work
implementing these methods on packaging the optoelectronic devices was successfully
conducted and described in detail. Packaging of the optoelectronic devices onto the OEMCM
was successfully performed. Electrical tests were successfully carried out on the
flip chip bonded VCSEL and Photodetector arrays. These results verified that the
devices attached on the MCM achieved good electrical performance and reliable
bonding. Finally, preliminary testing was conducted on the fully assembled OE-MCMs.
The aim was to initially power up the mixed signal chip (VCSEL driver), and then
observe the VCSEL output
Workshops at IMS2023
Lists future events that should be of interest to practitioners and researchers.Peer ReviewedPostprint (published version
Programmable photonics : an opportunity for an accessible large-volume PIC ecosystem
We look at the opportunities presented by the new concepts of generic programmable photonic integrated circuits (PIC) to deploy photonics on a larger scale. Programmable PICs consist of waveguide meshes of tunable couplers and phase shifters that can be reconfigured in software to define diverse functions and arbitrary connectivity between the input and output ports. Off-the-shelf programmable PICs can dramatically shorten the development time and deployment costs of new photonic products, as they bypass the design-fabrication cycle of a custom PIC. These chips, which actually consist of an entire technology stack of photonics, electronics packaging and software, can potentially be manufactured cheaper and in larger volumes than application-specific PICs. We look into the technology requirements of these generic programmable PICs and discuss the economy of scale. Finally, we make a qualitative analysis of the possible application spaces where generic programmable PICs can play an enabling role, especially to companies who do not have an in-depth background in PIC technology
Providing Bi-Directional, Analog, and Differential Signal Transmission Capability to an Electronic Prototyping Platform
RĂSUMĂ Les rĂ©seaux dâinterconnexions programmables (FPIN) se retrouvent largement utilisĂ©s dans plusieurs structures bien connues telles que les FPGA, les plateformes de prototypages ainsi que dans plusieurs architectures de rĂ©seaux intĂ©grĂ©s. Le but de la prĂ©sente thĂšse est dâamĂ©liorer la structure actuelle des FPIN ainsi que les plateformes de prototypages se basant sur cette technologie afin dây intĂ©grer dâautres fonctionnalitĂ©s telles que des interfaces pour les signaux bidirectionnels de type drain-ouvert, les signaux analogiques ou bien les signaux diïŹĂ©rentiels. Cette thĂšse prĂ©sente trois diïŹĂ©rents circuits qui ont Ă©tĂ© implĂ©mentĂ©s dans cette optique. Les interconnexions de ces trois circuits peuvent ĂȘtre reconfigurĂ©es pour supporter une interface de type bidirectionnelle drain-ouvert, de type analogique ou diïŹĂ©rentielle, le tout au travers un rĂ©seau dâinterconnexions configurable numĂ©rique unidirectionnel, ou FPIN. Le besoin dâune telle interface fut tout dâabord envisagĂ© dans le contexte du WaferBoard, qui consiste en une plateforme reconfigurable de prototypage pour les systĂšmes Ă©lectroniques. Le cĆur de ce WaferBoard consiste en un circuit intĂ©grĂ© Ă lâĂ©chelle dâune tranche entiĂšre de silicium, qui est constituĂ© dâune matrice bidimensionnelle de cellules. Une large partie de la surface disponible sâen retrouve dĂ©jĂ utilisĂ©e par des plots configurables (CIO), lâaiguillage des multiplexeurs du FPIN, des registres dĂ©diĂ©s Ă la chaine JTAG et dâautres circuiteries de contrĂŽle. De ce fait, il en devient primordial que les interfaces bidirectionnelle drain-ouvert, analogique et diïŹĂ©rentielle soit les plus compactes possibles. Puisque ces circuits dâinterfaces seront dĂ©diĂ©s pour une plateforme utilisant une tranche de silicium (wafer-scale), lâarchitecture de ces derniers doit ĂȘtre robuste en regard des variations de procĂ©dĂ©, de la tempĂ©rature ainsi que de lâalimentation. La premiĂšre contribution de cette thĂšse est lâĂ©laboration et la conception dâune interface de type drain-ouvert ainsi que de son support dâinterconnexion bidirectionnel utilisant un rĂ©seau numĂ©rique unidirectionnel Ă signalisation asymĂ©trique (Ă lâopposĂ© de la signalisation diïŹĂ©rentielle) FPIN. Lâinterface proposĂ©e peut interconnecter plusieurs nĆuds dâun FPIN. Ă lâaide de cette interface, le rĂ©seau dâinterconnexions peut imiter le comportement et le fonctionnement dâun bus de type drain-ouvert (ou collecteur-ouvert) (tel quâutilisĂ© par le protocole I2C). De ce fait, plusieurs plots de type drain-ouvert provenant dâune multitude de circuits-intĂ©grĂ©s (ICs) diïŹĂ©rents peuvent y ĂȘtre connectĂ©s au travers le FPIN Ă lâaide de lâinterface proposĂ©e.----------ABSTRACT Field programmable interconnection networks (FPINs) are ubiquitously found embedded in field-programmable gate arrays (FPGAs), in prototyping platforms, and in many Network-on-Chip architectures. The aim of this research was to augment the application domains of current FPIN-based prototyping and emulation platforms by supporting open-drain bi-directional signals, analog signals or diïŹerential signals. Three interface circuits have been elaborated and developed to that end in this thesis. These three interface circuits can support reconfigurable routing of open-drain bi-directional, analog and diïŹerential signals through an uni-directional digital FPIN. The need for such interface circuits were originally conceived in the context of the WaferBoard, a system prototyping platform. The core of the WaferBoard is a wafer-scale IC that is composed of a two dimensional array of unit cells. Available area was already over-utilized by the configurable I/O (CIO) buïŹers, crossbar multiplexers of the FPIN, registers of the JTAG chain, and other control circuits. Thus, the interface circuits for open-drain bi-directional, analog and diïŹerential signaling had to be made very compact. As the implementation of these interface circuits target âwafer-scaleâ integration, these interface circuits had to be very robust to parametric variations (process, temperature, power supply). The first contribution of this thesis is the elaboration and development of an open-drain interface circuit and a corresponding interconnect topology to support bi-directional communication through the uni-directional digital FPIN of prototyping platforms. The proposed interface can interconnect multiple nodes in a FPIN. With that interface, the interconnection network imitates the behavior of open-drain (or open-collector) buses (e.g., those following the I2C protocol). Thus, multiple open-drain I/Os from external integrated circuits (ICs) can be connected together through the FPIN by the proposed interface circuit. The interface that has been fabricated in a 0.13 ”m CMOS technology takes 65 ”m Ă 22 ”m per pin. Test results show that several instances of this interface can be interconnected through the proposed interconnect topology
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Hardware-Software Integrated Silicon Photonic Systems
Fabrication of integrated photonic devices and circuits in a CMOS-compatible process or foundry is the essence of the silicon photonic platform. Optical devices in this platform are enabled by the high index contrast between silicon and silicon on insulator. These devices offer potential benefits when integrated with existing and emerging high performance microelectronics. Integration of silicon photonics with small footprints and power-efficient and high-bandwidth operation has long been cited as a solution to existing issues in high performance interconnects for telecommunications and data communication. Stemming from this historic application in communications, new applications in sensing arrays, biochemistry, and even entertainment continue to grow. However, for many technologies to successfully adopt silicon photonics and reap the perceived benefits, the silicon photonic platform must extend toward development of a full ecosystem. Such extension includes implementation of low cost and robust electronic-photonic packaging techniques for all applications. In an ecosystem implemented with services ranging from device fabrication all the way to packaged products, ease-of-use and ease-of-deployment in systems that require many hardware and software components becomes possible.
With the onset of the Internet of Things (IoT), nearly all technologiesâsensors, compute, communication devices, etc.âpersist in systems with some level of localized or distributed software interaction. These interactions often require a level of networked communications. For silicon photonics to penetrate technologies comprising IoT, it is advantageous to implement such devices in a hardware-software integrated way. Meaning, all functionalities and interactions related to the silicon photonic devices are well defined in terms of the physicality of the hardware. This hardware is then abstracted into various levels of software as needed in the system. The power of hardware-software integration allows many of the piece-wise demonstrated functionalities of silicon photonics to easily translate to commercial implementation.
This work begins by briefly highlighting the challenges and solutions for transforming existing silicon photonic platforms to a full-fledged silicon photonic ecosystem. The highlighted solutions in development consist of tools for fabrication, testing, subsystem packaging, and system validation. Building off the knowledge of a silicon photonic ecosystem in development, this work continues by demonstrating various levels of hardware-software integration. These are primarily focused on silicon photonic interconnects.
The first hardware-software integration-focused portion of this work explores silicon microring-based devices as a key building block for greater silicon photonic subsystems. The microringâs sensitivity to thermal fluctuations is identified not as a flaw, but as a tool for functionalization. A logical control system is implemented to mitigate thermal effects that would normally render a microring resonator inoperable. The mechanism to control the microring is extended and abstracted with software programmability to offer wavelength routing as a network primitive. This functionality, available through hardware-software integration, offers the possibility for ubiquitous deployment of such microring devices in future photonic interconnection networks.
The second hardware-software integration-focused portion of this work explores dynamic silicon photonic switching devices and circuits. Specifically, interactions with and implications of high-speed data propagation and link layer control are demonstrated. The characteristics of photonic link setup include transients due to physical layer optical effects, latencies involved with initializing burst mode links, and optical link quality. The impacts on the functionalities and performance offered by photonic devices are explored. An optical network interface platform is devised using FPGAs to encapsulate hardware and software for controlling these characteristics using custom hardware description language, firmware, and software. A basic version of a silicon photonic network controller using FPGAs is used as a tool to demonstrate a highly scalable switch architecture using microring resonators. This architecture would not be possible without some semblance of this controller, combined with advanced electronic-photonic packaging. A more advanced deployment of the network interface platform is used to demonstrate a method for accelerating photonic links using out-of-band arbitration. A first demonstration of this platform is performed on a silicon photonic microring router network. A second demonstration is used to further explore the feasibility of full hardware-software integrated photonic device actuation, link layer control, and out-of-band arbitration. The demonstration is performed on a complete silicon photonic network with both spatial switching and wavelength routing functionalities.
The aforementioned hardware-software integration mechanisms are rigorously tested for data communications applications. Capabilities are shown for very reliable, low latency, and dynamic high-speed data delivery using silicon photonic devices. Applying these mechanisms to complete electronic-photonic packaged subsystems provides a strong path to commercial manifestations of functional silicon photonic devices
Photonic integrated circuit design in a foundry+fabless ecosystem
A foundry-based photonic ecosystem is expected to become necessary with increasing demand and adoption of photonics for commercial products. To make foundry-enabled photonics a real success, the photonic circuit design flow should adopt known concepts from analog and mixed signal electronics. Based on the similarities and differences between the existing photonic and the standardized electronics design flow, we project the needs and evolution of the photonic design flow, such as schematic driven design, accurate behavioral models, and yield prediction in the presence of fabrication variability
Conception d'un plot reconfigurable pour un réseau de distribution de puissance à l'échelle de la tranche en technologie CMOS
RĂSUMĂ De nos jours, les systĂšmes Ă©lectroniques sont dâune complexitĂ© croissante oĂč de nombreuses contraintes, autant techniques quâĂ©conomiques sont en jeux. La demande pour des circuits de puissance et de taille rĂ©duite, tout en conservant ou en amĂ©liorant les performances, est retentissante et ce tout en respectant des Ă©chĂ©anciers cruciaux de mise en marchĂ©. De nombreux efforts ont dĂ©jĂ Ă©tĂ© dĂ©ployĂ©s afin de rĂ©duire le temps ainsi que les coĂ»ts de conception, de prototypage et de dĂ©verminage de systĂšmes Ă©lectroniques complexes, mais aucune solution proposĂ©e jusquâĂ ce jour nâa su sâimposer pour traiter efficacement tous ces problĂšmes. Le travail de ce mĂ©moire a pour objectif la mise en Ćuvre dâun circuit intĂ©grĂ© destinĂ© Ă servir de plot configurable pour une plateforme de prototypage rapide de systĂšmes Ă©lectroniques. Cette plateforme se veut un outil pour concevoir des systĂšmes Ă©lectroniques complexes, pour ensuite les tester et les dĂ©verminer, le tout dans un temps raccourci. OĂč plusieurs mois Ă©taient requis, quelques jours sont maintenant suffisants. Le plot proposĂ© sera photo-rĂ©pĂ©tĂ© sur toute la surface dâune tranche de silicium au nombre de 1.3M et peut ĂȘtre configurĂ© en source de tension rĂ©gulĂ©e pour des valeurs typiques de 1.0, 1.5, 1.8, 2.0, 2.5 et 3.3 V, constituant ainsi un rĂ©seau de distribution de puissance trĂšs dense. Afin de propager un signal numĂ©rique provenant dâun rĂ©seau dâinterconnexions de la plateforme de prototypage, ce mĂȘme plot, Ă entrĂ©e et sortie unique, peut Ă©galement ĂȘtre programmĂ© en sortie numĂ©rique pour les mĂȘmes niveaux de tension Ă©numĂ©rĂ©s prĂ©cĂ©demment, ou bien en entrĂ©e numĂ©rique pour nâimporte quelle valeur de 1.0 Ă 3.3 V. Finalement, ce mĂȘme point dâaccĂšs doit Ă©galement pouvoir se comporter en masse ou en haute impĂ©dance et possĂ©der un systĂšme de dĂ©tection de contact entre plots voisins.----------ABSTRACT Nowadays, electronic systems integrate increasingly complex technical and economical constraints. The demand for less power hungry and smaller circuits, while offering improved performances, is crucial as much as time to market. There have been previous efforts to overcome the design, prototyping and debugging costs of high-end electronics systems, but none has succeeded in all the areas needed to revolutionize system design, prototyping and debugging. Our main objective, in this master thesis, is the implementation of integrated circuits dedicated to a platform for rapid prototyping of digital systems. The main purpose of this platform is to offer systems designers a tool to help designing, testing and debugging complex electronic systems in a shorter time frame. Where months where previously needed, days are now required. A programmable pad is presented, pad that will be photo-repeated by a number of up to 1.3 M times and can be configured in different output configurations. The first one is a power distribution network consisting of a very dense array of voltage regulators able to supply standard levels of 1.0, 1.5, 1.8, 2.0, 2.5 and 3.3 V. The propagation of digital signals from an interconnection network must be asserted by the same output of the proposed pad. It can be programmed as a digital output of the same standard voltage levels or as an input that complies with any signal varying from 1.0 to 3.3 V. Finally, the same access point can also be configured as a ground or floating node and possesses a contact detection circuitry to detect any short-circuits with its neighbour. The first contribution of this masterâs thesis consists of integrating multiple functions such as programmable voltage regulation and digital input/output into a common output. The second major contribution is the reduction of the needed silicon area and quiescent current by many orders of magnitude while offering better or equal performances regarding the hierarchical voltage regulator
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