Optimisation and parallelism in synchronous digital circuit simulators

Digital circuit simulation often requires a large amount of computation, resulting in long run times. We consider several techniques for optimising a brute force synchronous circuit simulator: an algorithm using an event queue that avoids recalculating quiescent parts of the circuit, a marking algorithm that is similar to the event queue but that avoids a central data structure, and a lazy algorithm that avoids calculating signals whose values are not needed. Two target architectures for the simulator are used: a sequential CPU, and a parallel GPGPU. The interactions between the different optimisations are discussed, and the performance is measured while the algorithms are simulating a simple but realistic scalable circuit

Digital system accurately controls velocity of electromechanical drive

Digital circuit accurately regulates electromechanical drive mechanism velocity. The gain and phase characteristics of digital circuits are relatively unimportant. Control accuracy depends only on the stability of the input signal frequency

A continued fraction generator for smooth pulse sequences

Digital circuit produces rational output pulse rate at fraction of continuous input pulse rate. Output pulses have average rate with least possible deviation from absolute correct time spacing. Circuit uses include frequency synthesizing, fraction generation, and approximation of irrational sequences

Overview of Hydra: a concurrent language for synchronous digital circuit design

Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and general design patterns that simplify the design of circuits with regular structure. Hydra specifications are concise, allowing the complete design of a computer system as a digital circuit within a few pages. This paper discusses the motivations behind Hydra, and illustrates the system with a significant portion of the design of a basic RISC processor

Frequency correction device uses digital circuitry

Signal acquisition and tracking system covering a wide range of frequencies uses a digital circuit to sample the frequency of an incoming signal and provide correction pulses to the voltage-controlled oscillator. The circuit can also sense the presence of a signal on any one of the input lines

Parallelism through Digital Circuit Design

Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed efficiently on ordinary parallel computers, including multicores. A class of data parallel algorithms is identified which have characteristics that make implementation on multiprocessors inefficient, but they are well suited for direct design as digital circuits. This leads to a programming model called circuit parallelism. The characteristics of circuit parallel algorithms are discussed, and a prototype system for supporting them is described

Reduction of quantization error in measurement of frequency

Method reduces quantization errors using new digital circuit. Circuit provides very high resolution (10 to the minus 2nd power to 10 to the minus 3rd power Hz) without high-speed counters. It lends itself to microminaturization and is simple to construct. Unknown frequency is compared to standard frequency by means of zero-crossing coincidence-detecting circuit