Defect site prediction based upon statistical analysis of fault signatures

Good failure analysis is the ability to determine the site of a circuit defect quickly and accurately. We propose a method for defect site prediction that is based on a site's probability of excitation, making no assumptions about the type of defect being analyzed. We do this by analyzing fault signatures and comparing them to the defect signature. We use this information to construct an ordered list of sites that are likely to be the site of the defect

An efficient logic fault diagnosis framework based on effect-cause approach

Fault diagnosis plays an important role in improving the circuit design process and the manufacturing yield. With the increasing number of gates in modern circuits, determining the source of failure in a defective circuit is becoming more and more challenging. In this research, we present an efficient effect-cause diagnosis framework for combinational VLSI circuits. The framework consists of three stages to obtain an accurate and reasonably precise diagnosis. First, an improved critical path tracing algorithm is proposed to identify an initial suspect list by backtracing from faulty primary outputs toward primary inputs. Compared to the traditional critical path tracing approach, our algorithm is faster and exact. Second, a novel probabilistic ranking model is applied to rank the suspects so that the most suspicious one will be ranked at or near the top. Several fast filtering methods are used to prune unrelated suspects. Finally, to refine the diagnosis, fault simulation is performed on the top suspect nets using several common fault models. The difference between the observed faulty behavior and the simulated behavior is used to rank each suspect. Experimental results on ISCAS85 benchmark circuits show that this diagnosis approach is efficient both in terms of memory space and CPU time and the diagnosis results are accurate and reasonably precise

An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits

Per-test diagnosis based on the X-fault model is an effective approach for a circuit with physical defects of nondeterministic logic behavior. However, the extensive use of vias and the unpredictable order relation among threshold voltages at fanout branches, both being typical phenomena in a deep-submicron circuit, have not been fully addressed by conventional per-test X-fault diagnosis. To solve these problems, this paper proposes an improved per-test X-fault diagnosis method, featuring (1) an extended X-fault model to handle vias and (2) occurrence probabilities of logic behavior for a physical defect to handle the unpredictable relation among threshold voltages. Experimental result show the effectiveness of the proposed method.7th Workshop on RTL and High Level Testing (WRTLT`06), November 23-24, 2006, Fukuoka, Japa

Diagnosis of systematic defects based on design-for-manufacturability guidelines

All products in the Very-Large-Scale-Integrated-Circuit (VLSIC) industry go through three major stages of production - Design, Verification and Manufacturing. Unfortunately, neither of these stages are truly perfect, hence we need two more sub-stages of manufacturing, namely Testing and Defect Diagnosis to prevent imperfections in ICs. Testing is used to generate test vectors to validate the functionality of the Device-under-Test (DUT), and Defect Diagnosis is the process of identifying the root-cause of a failing chip, i.e., the location and nature of defect. Systematic defects are unintended structural and material changes at specific locations with a higher probability of failure due to repeating manufacturing imperfections. While Design-For-Manufacturability (DFM) guidelines are not always applied due to limited resources like circuit area and design time, enforcing these guidelines helps in ensuring sufficient product yields by preventing systematic defects. However, even if the DFM guidelines are strictly enforced, systematic defects may still occur as complete information about the process and manufacturing is not available due to reducing available time-to-market for chips. ^ An earlier work used DFM guidelines as a basis for modeling of defects, and diagnostic test generation. Under this framework, a circuit is processed to identify layout locations that violate DFM rules. Next, these coordinates are mapped and translated to faults based on different fault models including stuck-at-faults, bridging faults and transition faults. ^ The goal of this thesis is to perform systematic defect diagnosis and analyze the accuracy of diagnosis under the same DFM framework. Thus, systematic defect candidates are generated from DFM guidelines and the generated faultlist is used to perform diagnosis. Because defects may not always be systematic, a new heuristic to dynamically switch between DFM and non-DFM faultlists has also been implemented. This presents us with the best option to follow to further optimize the accuracy of diagnosis. The results demonstrate that the DFM framework can be used to improve the accuracy of diagnosis with minimal resource requirements

Interconnect yield analysis and fault tolerance for field programmable gate arrays

Imperial Users onl

Test and Diagnosis of Integrated Circuits

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users, the manufacturing process is becoming finer and denser, making chips more prone to defects.The work presented in the HDR manuscript addresses the challenges of test and diagnosis of integrated circuits. It covers:- Power aware test;- Test of Low Power Devices;- Fault Diagnosis of digital circuits

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Investigations into the feasibility of an on-line test methodology

This thesis aims to understand how information coding and the protocol that it supports can affect the characteristics of electronic circuits. More specifically, it investigates an on-line test methodology called IFIS (If it Fails It Stops) and its impact on the design, implementation and subsequent characteristics of circuits intended for application specific lC (ASIC) technology. The first study investigates the influences of information coding and protocol on the characteristics of IFIS systems. The second study investigates methods of circuit design applicable to IFIS cells and identifies the· technique possessing the characteristics most suitable for on-line testing. The third study investigates the characteristics of a 'real-life' commercial UART re-engineered using the techniques resulting from the previous two studies. The final study investigates the effects of the halting properties endowed by the protocol on failure diagnosis within IFIS systems. The outcome of this work is an identification and characterisation of the factors that influence behaviour, implementation costs and the ability to test and diagnose IFIS designs