Bounded Model Checking of State-Space Digital Systems: The Impact of Finite Word-Length Effects on the Implementation of Fixed-Point Digital Controllers Based on State-Space Modeling

The extensive use of digital controllers demands a growing effort to prevent design errors that appear due to finite-word length (FWL) effects. However, there is still a gap, regarding verification tools and methodologies to check implementation aspects of control systems. Thus, the present paper describes an approach, which employs bounded model checking (BMC) techniques, to verify fixed-point digital controllers represented by state-space equations. The experimental results demonstrate the sensitivity of such systems to FWL effects and the effectiveness of the proposed approach to detect them. To the best of my knowledge, this is the first contribution tackling formal verification through BMC of fixed-point state-space digital controllers.Comment: International Symposium on the Foundations of Software Engineering 201

Filter-Based Fading Channel Modeling

A channel simulator is an essential component in the development and accurate performance evaluation of wireless systems. A key technique for producing statistically accurate fading variates is to shape the flat spectrum of Gaussian variates using digital filters. This paper addresses various challenges when designing real and complex spectrum shaping filters with quantized coefficients for efficient realization of both isotropic and nonisotropic fading channels. An iterative algorithm for designing stable complex infinite impulse response (IIR) filters with fixed-point coefficients is presented. The performance of the proposed filter design algorithm is verified with 16-bit fixed-point simulations of two example fading filters

Wordlength optimization for linear digital signal processing

Published versio

Fir filter design for area efficient implementation /

In this dissertation, a variable precision algorithm based on sensitivity analysis is proposed for reducing the wordlength of the coefficients and/or the number of nonzero bits of the coefficients to reduce the complexity required in the implementation. Further space savings is possible if the proposed algorithm is associated with our optimal structures and derived scaling algorithm. We also propose a structure to synthesize FIR filters using the improved prefilter equalizer structure with arbitrary bandwidth, and our proposed filter structure reduces the area required. Our improved design is targeted at improving the prefilters based on interpolated FIR filter and frequency masking design and aims to provide a sharp transition-band as well as increasing the stopband attenuation. We use an equalizer designed to compensate the prefilter performance. In this dissertation, we propose a systematic procedure for designing FIR filters implementations. Our method yields a good design with low coefficient sensitivity and small order while satisfying design specifications. The resulting hardware implementation is suitable for use in custom hardware such as VLSI and Field Programmable Gate Arrays (FPGAs).FIR filters are preferred for many Digital Signal Processing applications as they have several advantages over IIR filters such as the possibility of exact linear phase, shorter required wordlength and guaranteed stability. However, FIR filter applications impose several challenges on the implementations of the systems, especially in demanding considerably more arithmetic operations and hardware components. This dissertation focuses on the design and implementation of FIR filters in hardware to reduce the space required without loss of performance

Design of approximate overclocked datapath

Embedded applications can often demand stringent latency requirements. While high degrees of parallelism within custom FPGA-based accelerators may help to some extent, it may also be necessary to limit the precision used in the datapath to boost the operating frequency of the implementation. However, by reducing the precision, the engineer introduces quantisation error into the design. In this thesis, we describe an alternative circuit design methodology when considering trade-offs between accuracy, performance and silicon area. We compare two different approaches that could trade accuracy for performance. One is the traditional approach where the precision used in the datapath is limited to meet a target latency. The other is a proposed new approach which simply allows the datapath to operate without timing closure. We demonstrate analytically and experimentally that for many applications it would be preferable to simply overclock the design and accept that timing violations may arise. Since the errors introduced by timing violations occur rarely, they will cause less noise than quantisation errors. Furthermore, we show that conventional forms of computer arithmetic do not fail gracefully when pushed beyond the deterministic clocking region. In this thesis we take a fresh look at Online Arithmetic, originally proposed for digit serial operation, and synthesize unrolled digit parallel online arithmetic operators to allow for graceful degradation. We quantify the impact of timing violations on key arithmetic primitives, and show that substantial performance benefits can be obtained in comparison to binary arithmetic. Since timing errors are caused by long carry chains, these result in errors in least significant digits with online arithmetic, causing less impact than conventional implementations.Open Acces

Improving Reliability and Assessing Performance of Global Navigation Satellite System Precise Point Positioning Ambiguity Resolution

Conventional Precise Point Positioning (PPP) has always required a relatively long initialization period (few tens of minutes at least) for the carrier-phase ambiguities to converge to constant values and for the solution to reach its optimal precision. The classical PPP convergence period is primarily caused by the estimation of the carrier-phase ambiguity from the relatively noisy pseudoranges and the estimation of atmospheric delay. If the underlying integer nature of the ambiguity is known, it can be resolved, thereby reducing the convergence time of conventional PPP. To recover the underlying integer nature of the carrier-phase ambiguities, different strategies for mitigating the satellite and receiver dependent equipment delays have been developed, and products made publicly available to enable ambiguity resolution without any baseline restrictions. There has been limited research within the scope of interoperability of the products, combining the products to improve reliability and assessment of ambiguity resolution within the scope of being an integrity indicator. This study seeks to develop strategies to enable each of these and examine their feasibility. The advantage of interoperability of the different PPP ambiguity resolution (PPP-AR) products would be to permit the PPP user to transform independently generated PPP-AR products to obtain multiple fixed solutions of comparable precision and accuracy. The ability to provide multiple solutions would increase the reliability of the solution for, e.g., real-time processing: if there were an outage in the generation of the PPP-AR products, the user could instantly switch streams to a different provider. The satellite clock combinations routinely produced within the International GNSS Service (IGS) currently disregard that analysis centers (ACs) provide products which enable ambiguity resolution. Users have been expected to choose either an IGS product which is a combined product from multiple ACs or select an individual AC solution which provides products that enable PPP-AR. The goal of the novel research presented was to develop and test a robust satellite clock combination preserving the integer nature of the carrier-phase ambiguities at the user end. mm-level differences were noted, which was expected as the strength lies mainly in its reliability and stable median performance and the combined product is better than or equivalent to any single ACs product in the combination process. As have been shown in relative positioning and PPP-AR, ambiguity resolution is critical for enabling cm-level positioning. However, what if specifications where at the few dm-level, such as 10 cm and 20 cm horizontal what role does ambiguity resolution play? The role of ambiguity resolution relies primarily on what are the user specifications. If the user specifications are at the few cm-level, ambiguity resolution is an asset as it improves convergence and solution stability. Whereas, if the users specification is at the few dm-level, ambiguity resolution offers limited improvement over the float solution. If the user has the resources to perform ambiguity resolution, even when the specifications are at the few dm-level, it should be utilized

Analysis of Nonlinear Behaviors, Design and Control of Sigma Delta Modulators

M PhilSigma delta modulators (SDMs) have been widely applied in analogue-to-digital (A/D) conversion for many years. SDMs are becoming more and more popular in power electronic circuits because it can be viewed and applied as oversampled A/D converters with low resolution quantizers. The basic structure of an SDM under analytical investigation consists of a loop filter and a low bit quantizer connected by a negative feedback loop. Although there are numerous advantages of SDMs over other A/D converters, the application of SDMs is limited by the unboundedness of the system states and their nonlinear behaviors. It was found that complex dynamical behaviors exist in low bit SDMs, and for a bandpass SDM, the state space dynamics can be represented by elliptic fractal patterns confined within two trapezoidal regions. In all, there are three types of nonlinear behaviors, namely fixed point, limit cycle and chaotic behaviors. Related to the unboundedness issue, divergent behavior of system states is also a commonly discovered phenomenon. Consequently, how to design and control the SDM so that the system states are bounded and the unwanted nonlinear behaviors are avoided is a hot research topic worthy of investigated. In our investigation, we perform analysis on such complex behaviors and determine a control strategy to maintain the boundedness of the system states and avoid the occurrence of limit cycle behavior. For the design problem, we impose constraints based on the performance of an SDM and determine an optimal design for the SDM. The results are significantly better than the existing approaches

New Approach of Indoor and Outdoor Localization Systems

Accurate determination of the mobile position constitutes the basis of many new applications. This book provides a detailed account of wireless systems for positioning, signal processing, radio localization techniques (Time Difference Of Arrival), performances evaluation, and localization applications. The first section is dedicated to Satellite systems for positioning like GPS, GNSS. The second section addresses the localization applications using the wireless sensor networks. Some techniques are introduced for localization systems, especially for indoor positioning, such as Ultra Wide Band (UWB), WIFI. The last section is dedicated to Coupled GPS and other sensors. Some results of simulations, implementation and tests are given to help readers grasp the presented techniques. This is an ideal book for students, PhD students, academics and engineers in the field of Communication, localization & Signal Processing, especially in indoor and outdoor localization domains