Concurrent Image Processing Executive (CIPE)

The design and implementation of a Concurrent Image Processing Executive (CIPE), which is intended to become the support system software for a prototype high performance science analysis workstation are discussed. The target machine for this software is a JPL/Caltech Mark IIIfp Hypercube hosted by either a MASSCOMP 5600 or a Sun-3, Sun-4 workstation; however, the design will accommodate other concurrent machines of similar architecture, i.e., local memory, multiple-instruction-multiple-data (MIMD) machines. The CIPE system provides both a multimode user interface and an applications programmer interface, and has been designed around four loosely coupled modules; (1) user interface, (2) host-resident executive, (3) hypercube-resident executive, and (4) application functions. The loose coupling between modules allows modification of a particular module without significantly affecting the other modules in the system. In order to enhance hypercube memory utilization and to allow expansion of image processing capabilities, a specialized program management method, incremental loading, was devised. To minimize data transfer between host and hypercube a data management method which distributes, redistributes, and tracks data set information was implemented

IMPLEMENTATION OF A LOCALIZATION-ORIENTED HRI FOR WALKING ROBOTS IN THE ROBOCUP ENVIRONMENT

This paper presents the design and implementation of a human–robot interface capable of evaluating robot localization performance and maintaining full control of robot behaviors in the RoboCup domain. The system consists of legged robots, behavior modules, an overhead visual tracking system, and a graphic user interface. A human–robot communication framework is designed for executing cooperative and competitive processing tasks between users and robots by using object oriented and modularized software architecture, operability, and functionality. Some experimental results are presented to show the performance of the proposed system based on simulated and real-time information. </jats:p

Concurrent Image Processing Executive (CIPE). Volume 1: Design overview

The design and implementation of a Concurrent Image Processing Executive (CIPE), which is intended to become the support system software for a prototype high performance science analysis workstation are described. The target machine for this software is a JPL/Caltech Mark 3fp Hypercube hosted by either a MASSCOMP 5600 or a Sun-3, Sun-4 workstation; however, the design will accommodate other concurrent machines of similar architecture, i.e., local memory, multiple-instruction-multiple-data (MIMD) machines. The CIPE system provides both a multimode user interface and an applications programmer interface, and has been designed around four loosely coupled modules: user interface, host-resident executive, hypercube-resident executive, and application functions. The loose coupling between modules allows modification of a particular module without significantly affecting the other modules in the system. In order to enhance hypercube memory utilization and to allow expansion of image processing capabilities, a specialized program management method, incremental loading, was devised. To minimize data transfer between host and hypercube, a data management method which distributes, redistributes, and tracks data set information was implemented. The data management also allows data sharing among application programs. The CIPE software architecture provides a flexible environment for scientific analysis of complex remote sensing image data, such as planetary data and imaging spectrometry, utilizing state-of-the-art concurrent computation capabilities

A CLIPS-based tool for aircraft pilot-vehicle interface design

The Pilot-Vehicle Interface of modern aircraft is the cognitive, sensory, and psychomotor link between the pilot, the avionics modules, and all other systems on board the aircraft. To assist pilot-vehicle interface designers, a C Language Integrated Production System (CLIPS) based tool was developed that allows design information to be stored in a table that can be modified by rules representing design knowledge. Developed for the Apple Macintosh, the tool allows users without any CLIPS programming experience to form simple rules using a point and click interface

Development of a novel 3D simulation modelling system for distributed manufacturing

This paper describes a novel 3D simulation modelling system for supporting our distributed machine design and control paradigm with respect to simulating and emulating machine behaviour on the Internet. The system has been designed and implemented using Java2D and Java3D. An easy assembly concept of drag-and-drop assembly has been realised and implemented by the introduction of new connection features (unified interface assembly features) between two assembly components (modules). The system comprises a hierarchical geometric modeller, a behavioural editor, and two assemblers. During modelling, designers can combine basic modelling primitives with general extrusions and integrate CAD geometric models into simulation models. Each simulation component (module) model can be visualised and animated in VRML browsers. It is reusable. This makes machine design re-configurable and flexible. A case study example is given to support our conclusions

Modular Digital Game System

This project created an Application Programming Interface (API) for a simulated modular digital game system. Each module consists of a triangle that displays colors at the center and edges, monitors an input and signals from the surrounding modules, and communicates with a computer controller. The API allows users to develop game programs for the system. The simulation runs the game files and displays the results. The focus was on practical coding and design of an instructional game system. The challenges in creating such a system provided a valuable learning environment for us in the areas of user interface design, system tool management and design, human computer interaction, and designing educational platforms

DEVELOPING A MOTOROLA 68000 TRAINING BOARD

The aim of this project is to build a Motorola 68000 microprocessor training board using modular approach to aid the teaching and learning process for the microprocessor subject in Universiti Teknologi Petronas (UTP). The board is designed in modular approach to nurture more understanding among the students on the system itself. The final system consists of 3 different separated cards; the central processing unit (CPU) card, the memory card, and a serial/parallel interface card and a backplane. Wire wrapping method is used to build the training board. This project involves circuit design study, parts substitution study, and the board construction itself Basically, the board features a Motorola 68000 microprocessor, 10-MHz crystal clock, buffer circuits, memory decoder circuits, EPROM modules, SRAM modules, serial interface, and parallel interface. This board can be connected to a personal computer (PC) through serial interface for program downloading purposes, and the output is connected through the parallel interface available on-board. It is envisaged that the final system would be utilized as a learning tool for the microprocessor course (EAB2023)

TIM (TTC Interface Module) for ATLAS SCT & PIXEL Read Out Electronics

The design, functionality, description of hardware and firmware and preliminary results of the ROD ( Read Out Driver) System Tests of the TIM (TTC Interface Module) are described.The TIM is the standard SCT and PIXEL detector interface module to the ATLAS Level-1 Trigger, using the LHC-standard TTC (Timing, Trigger and Control) system.TIM designed and built during 1999 and 2000 and two prototypes have been in use since then (Fig. 1). More modules are being built this year to allow for more tests of the ROD system at different sites around the world

Simulation analysis of a microcomputer-based, low-cost Omega navigation system

The current status of research on a proposed micro-computer-based, low-cost Omega Navigation System (ONS) is described. The design approach emphasizes minimum hardware, maximum software, and the use of a low-cost, commercially-available microcomputer. Currently under investigation is the implementation of a low-cost navigation processor and its interface with an omega sensor to complete the hardware-based ONS. Sensor processor functions are simulated to determine how many of the sensor processor functions can be handled by innovative software. An input data base of live Omega ground and flight test data was created. The Omega sensor and microcomputer interface modules used to collect the data are functionally described. Automatic synchronization to the Omega transmission pattern is described as an example of the algorithms developed using this data base

Advanced information processing system: Input/output system services

The functional requirements and detailed specifications for the Input/Output (I/O) Systems Services of the Advanced Information Processing System (AIPS) are discussed. The introductory section is provided to outline the overall architecture and functional requirements of the AIPS system. Section 1.1 gives a brief overview of the AIPS architecture as well as a detailed description of the AIPS fault tolerant network architecture, while section 1.2 provides an introduction to the AIPS systems software. Sections 2 and 3 describe the functional requirements and design and detailed specifications of the I/O User Interface and Communications Management modules of the I/O System Services, respectively. Section 4 illustrates the use of the I/O System Services, while Section 5 concludes with a summary of results and suggestions for future work in this area