Quantum Cost Optimization for Reversible Sequential Circuit

Reversible sequential circuits are going to be the significant memory blocks for the forthcoming computing devices for their ultra low power consumption. Therefore design of various types of latches has been considered a major objective for the researchers quite a long time. In this paper we proposed efficient design of reversible sequential circuits that are optimized in terms of quantum cost, delay and garbage outputs. For this we proposed a new 3*3 reversible gate called SAM gate and we then design efficient sequential circuits using SAM gate along with some of the basic reversible logic gates.Comment: Quantum 4.12 (2013). arXiv admin note: substantial text overlap with arXiv:1312.735

A review on reversible logic gates

In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.   Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic

Reducing Delay and Quantum Cost in the Novel Design of Reversible Memory Elements

AbstractIn a computational model, that uses transitions from one state of the abstract machine to another, a necessary condition for reversibility is that, the relation of the mapping from states to their successors must be one-to-one. In these works, the primary focus of design is to optimize number of reversible gates and garbage outputs. The calculation of number of gates is not a good option to check the complexity of a circuit as each gate has different architectural complexity decided by a parameter called quantum cost. Delay, hardly addressed in the existing works available in literature, is another good parameter to be optimized for fast reversible computation. In this work, we have presented novel designs of basic sequential circuits like latch that are optimum in terms of delay, quantum cost and garbage. We have also demonstrated quantum cost efficient D-FF, SR-FF, JK-FF & T-FF, along with their master slave configurations

DESIGN OF AN EFFICIENT REVERSIBLE LOGIC BASED BIDIRECTIONAL BARREL SHIFTER

Embedded digital signal processors and general purpose processors will use barrel shifters to manipulate data. This paper will present the design of the barrel shifter that performs logical shift right, arithmetic shift right, rotate right, logical shift left, arithmetic shift left, and rotate left operations. The main objective of the upcoming designs is to increase the performance without proportional increase in power consumption. In this regard reversible logic has become most popular technology in the field of low power computing, optical computing, quantum computing and other computing technologies. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated

DESIGN METHODOLOGY OF BIDIRECTIONAL BARREL SHIFTER BASED ON REVERSIBLE LOGIC

Data shifting is required in many key computer operations from address decoding to computer arithmetic. Full barrel shifters are often on the critical path, which has led most research to be directed toward speed optimizations. With the advent of quantum computer and reversible logic, design and implementation of all devices in this logic has received more attention. Rotating and data shifting are required in many operations such as logical and arithmetic operations, indexing and address decoding etc. Hence barrel shifters which can shift and rotate multiple bits in a single cycle have become a common choice of design for high speed applications. The design has been done using reversible fredkin and feynman gates. In the design the 2:1 mux can be implemented by fredkin gate which reduce quantum cost, number of ancilla bits and number of garbage outputs. The feynman gate will remove the fanout. By comparing the quantum cost, number of ancilla bits and number of garbage outputs the design is evaluated

COMPARATIVE ANALYSIS OF 4-BIT AND 8-BIT REVERSIBLE BARREL SHIFTER DESIGNS USING REVKIT

ABSTRACT In the recent years, reversible logic has emerged as a viable approach in power optimization and also has found its importance in low power CMOS, quantum computing, nanotechnology, and optical computing. The main challenge in reversible circuits is to optimize the quantum cost, time delay and the garbage outputs associated with the reversible circuit. 'RevKit' in recent years has become a popular and powerful tool for design visualization, implementation and analysis in reversible computing. In this work, we have implemented the design of reversible 4-bit and 8-bit barrel shifter circuits in RevKit and results are analyzed in terms of quantum cost, delay, garbage outputs, gate count, line count and transistor cost. Further, the simulation results have been documented and tabulated to facilitate a comparative study with conventional designs. Keywords: reversible circuits, barrel shifters, quantum cost, time delay, garbage output, RevKit. INTRODUCTION In irreversible logic computations [1], each bit of information lost generates kTln2 joules of heat energy, where k is Boltzmann's constant and T is the absolute temperature at which the computation is performed. Thus, the amount of energy dissipated in a system bears a direct relationship to the number of bits erased during the computation. The kTln2 energy dissipation can be avoided [2] if a computation is carried out in a reversible manner Rotating and shifting data in a single cycle are required in several applications like efficient computations and arithmetic operations. Barrel shifters, more suitable for this kind of operations, since, it is capable of shifting or rotating the inputs in a single cycle and find great importance in the digital signal processing computation. In reversible system information is not erased. The number of inputs and outputs are equal in reversible gates, which means that the input stage can always be retained from the output stage. Thus, such an implementation of reversible barrel shifter will be highly efficient when compared to any conventional design in terms of time delay, garbage output or the quantum cost associated with such a structure. The majority of the work that currently exists in literature focuses on optimizing the reversible sequential designs in terms of number of reversible gates and garbage outputs using functional verification. A few prior works have used design tools such as RevKi

A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic

Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. The ALU circuit has been simulated on Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. This 2-bit ALU using reversible logic is useful for the designs of low power loss systems