Synchronisation in sampled receivers for narrowband digital modulation schemes.

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Enhancing mobile services with DVB-S2X superframing

DVB-S2X is the cornerstone for satellite communication standards forming the state of the art of broadband satellite waveforms. In this paper, we propose new application scenarios and advanced techniques, including a reference design implementing superframing, predistortion, a robust synchronization chain, and a plug-and-play channel interleaver. We demonstrate by means of software simulations and hardware tests that the DVB-S2X can be a common technology enabler for land-mobile, aeronautical, and maritime satellite scenarios in addition to the more traditional VSAT scenario, even in very challenging conditions (eg, very low signal-to-noise ratio)

Synchronization in all-digital QAM receivers

The recent advance in Field Programmable Gate Array (FPGA) technology has been largely embraced by the communication industry, which views this technology as an effective and economical alternative to the design of Application Specific Integrated Circuits (ASICs). The primary reasons for switching to FPGAs are lower development and non-recurring engineering costs, the flexibility to design to a preliminary standard and adapt the design as the standard evolves, as well as the option of performing software updates in the field. A sector with strong interest in FPGAs is the coaxial cable TV/Internet distribution industry. The creation of soft preliminary standards by the standards organization governing the industry has been the main catalyst for the massive adoption of FPGAs by small to medium size companies, which see this technology as an opportunity to compete in this open market. Both the circuit speed and the economy of FPGA technology depend upon using algorithms that map efficiently into its fabric. Often it is prudent to sacrifice performance to improve either clock speed or economy when developing with FPGAs. The purpose of this research is to both revise and devise synchronization algorithms / structures for cable digital receivers that are to be implemented in FPGA. The main communication scheme used by the coaxial cable distribution industry is digital Quadrature Amplitude Modulation (QAM). The problem of synchronizing to the QAM signal in the receiver is not a new topic and several synchronization-related circuits, which were devised with ASICs implementation in mind, can be found in the open literature. Of interest in this thesis is the non-data-aided digital timing synchronizer that was proposed by D'Andrea to recover timing with no knowledge of the transmitted data. Accurate timing estimation was achieved by reshaping the received signal with a prefilter prior to estimating the timing. A problem with D'Andrea's synchronizer is that the prefilter for reshaping the signal is a relatively long Finite Impulse Response (FIR) filter, whose implementation requires a large number of multipliers. This may not have been an issue with ASICs in as much as the number of hardwired multipliers on a chip is not limited as it is in an FPGA chip. One contribution in this research is to propose an alternative to D'Andrea's synchronizer by replacing the long FIR filter with two single-pole Infinite Impulse Response (IIR) filters that are directly placed inside the timing recovery loop. This novel architecture, which drastically reduces the number of multipliers, is well suited for FPGA implementation. Non-data-aided feedforward synchronizers, which use the same prefilter as D'Andrea's synchronizer, have been receiving significant attention in recent years. Detailed performance analysis for these synchronizers can be found in the open literature. These synchronizers have the advantage of using a feedfordward structure rather than a feedback structure, as it is the case in D'Andrea's synchronizer, to estimate the timing. While D'Andrea's synchronizer has an advantage in performance over a non-data-aided feedforward synchronizer, this has not been reported in the literature. In this thesis a second contribution consists of thoroughly analyzing the steady state timing jitter in D'Andrea synchronizer by deriving a closed-form expression for the noise power spectrum and a simple equation to estimate the timing jitter variance. A third contribution is a novel low-complexity and fast acquisition coherent detector for the detection of Quadrature Phase Shift Keying (QPSK) (i.e., 4-QAM) symbols. This detector performs carrier phase synchronization much faster than a conventional coherent detector. The acquisition time is comparable to that of a differential detector. The fast acquisition comes at the expense of phase jitter, and the end result is a 1 dB performance loss over theoretical coherent detection. This detector can be used in place of the differential detector with no economic penalty. Doing so yields a performance advantage of about 2 dB over differential detection

Nuevas implementaciones digitales de sincronismos de BIT y portadora en Módem CPM

Las técnicas digitales aplicadas a receptores y transmisores están imponiéndose a las convencionales técnicas analógicas por las diversas ventajas que supone. En este sentido se impone una investigación con el fin de desarrollar dichas técnicas o mejorarlas en algún aspecto. La idea principal que engloba esta Tesis Doctoral es precisamente la indagación en algunas de dichas técnicas, su análisis, caracterización y aplicación a dos casos concretos. En un primer momento se han caracterizado dos canales de comunicaciones donde se pretende hacer uso de las técnicas a desarrollar. Este es un aspecto importante para conocer las condiciones reales en que deberán operar los algoritmos y cómo pueden verse afectados. Los canales que se caracterizan corresponden al establecido para satélites de órbita baja y el formado por las líneas de distribución de media tensión. En segundo lugar se ha realizado una descripción del tipo de modulación que se pretende emplear en los canales (GMSK) y se ha tratado de obtener una estructura del receptor con la menor complejidad posible. Basándose en una descripción de la modulación mediante una aproximación que da lugar a un modelo lineal, se desarrolla un receptor lineal de estructura sencilla y con unas prestaciones razonables, suponiendo una gran ventaja. Una vez descrita la estructura del receptor en el cual se van a emplear los algoritmos, se tratan dos aspectos cruciales en los receptores: la sincronización de portadora y el sincronismo de bit. Las técnicas que se desarrollan parten de la idea de su integración en un receptor totalmente digital. Son técnicas de procesado digital de señales. Se aborda el problema de la sincronización de portadora dando como solución diversos algoritmos que operan basándose en diferentes principios y obtienen diferentes características. Se destacan las ventajas e inconvenientes de cada uno de ellos y se presentan resultados de su funcionamiento. Respecto a la sincronización de bit se aborda el caso del empleo de interpoladores basados en la interpolación matemática para tal fin. Se trata de una técnica de cambio de velocidad de muestreo de forma dinámica para que las muestras de salida estén situadas en los instantes de muestreo óptimos. El interpolador lleva asociados un detector de error de sincronismo de bit y un sistema de control del interpolador. En el caso del detector de error se ha partido de la premisa de obtener un detector sencillo, de baja carga computacional y eficiente. El algoritmo se ha basado en el cruce por cero de la señal en las alternancias