Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

DESIGN OF ONCHIP LOW DROPOUT (LDO) REGULATOR FOR POWER MANAGEMENT APPLICATION

A low dropout regulator is proposed in this paper. The regulator is designed with classic five pack model to decrease the number of devices and make the design compact and also reduce the power consumption. The system is designed and simulated in cadence virtuoso environment under 180nm technology node. Three models of LDO is proposed in this paper, with all having same error amplifier but with small variations. The advantages and disadvantages of each model will be discussed in the paper. The LDOs have linear characteristic over a good input range. It has good transient response to load variation.Â

A Ringamp-Assisted, Output Capacitor-less Analog CMOS Low-Dropout Voltage Regulator

Continued advancements in state-of-the-art integrated circuits have furthered trends toward higher computational performance and increased functionality within smaller circuit area footprints, all while improving power efficiencies to meet the demands of mobile and battery-powered applications. A significant portion of these advancements have been enabled by continued scaling of CMOS technology into smaller process node sizes, facilitating faster digital systems and power optimized computation. However, this scaling has degraded classic analog amplifying circuit structures with reduced voltage headroom and lower device output resistance; and thus, lower available intrinsic gain. This work investigates these trends and their impact for fine-grain Low-Dropout (LDO) Voltage Regulators, leading to a presented design methodology and implementation of a state-of-the-art Ringamp-Assisted, Output Capacitor-less Analog CMOS LDO Voltage Regulator capable of both power scaling and process node scaling for general SoC applications

Design of a Low Power External Capacitor-Less Low-Dropout Regulator with Gain-Compensated Error Amplifier

This thesis introduces a gain-compensated external capacitor-less low-dropout voltage regulator with total 5.7 uA quiescent current at all load conditions. The two-stage gain-compensated error amplifier is implemented with a cross-couple pair negative resistor to make the LDO achieve higher gain (> 50 dB) with very low bias current (< 1.3 uA). The LDO can achieve 52 dB loop gain at no load condition, 64 dB at 1 mA and 54 dB at 100 mA load. During transients (0 A to 100 mA) the undershoot is optimized to 98.6 mV with 100 ns rising and falling time through a differentiator circuit to boost the LDO’s transient response. The phase margin of the proposed LDO is 55◦ at 1 mA and 79.27◦ at max load (100 mA). Figure of merit (FOM) of this work is 2.79 fs which is very small

A sub-1 V, 26 μw, low-output-impedance CMOS bandgap reference with a low dropout or source follower mode

We present a low-power bandgap reference (BGR), functional from sub-1 V to 5 V supply voltage with either a low dropout (LDO) regulator or source follower (SF) output stage, denoted as the LDO or SF mode, in a 0.5-μm standard digital CMOS process with V tn≈ 0.6 V and |V tp| ≈ 0.7 V at 27 °C. Both modes operate at sub-1 V under zero load with a power consumption of around 26 μW. At 1 V (1.1 V) supply, the LDO (SF) mode provides an output current up to 1.1 mA (0.35 mA), a load regulation of ±8.5 mV/mA (±33 mV/mA) with approximately 10 μ s transient, a line regulation of ±4.2 mV/V (±50μV/V), and a temperature compensated reference voltage of 0.228 V (0.235 V) with a temperature coefficient around 34 ppm/° C from -20°C to 120 °C. At 1.5 V supply, the LDO (SF) mode can further drive up to 9.6 mA (3.2 mA) before the reference voltage falls to 90% of its nominal value. Such low-supply-voltage and high-current-driving BGR in standard digital CMOS processes is highly useful in portable and switching applications. © 2010 IEEE.published_or_final_versio

Power Supply Rejection Improvement Techniques In Low Drop-Out Voltage Regulators

Low drop out (LDO) voltage regulators are widely used for post regulating the switching ripples generated by the switched mode power supplies (SMPS). Due to demand for portable applications, industry is pushing for complete system on chip power management solutions. Hence, the switching frequencies of the SMPS are increasing to allow higher level of integration. Therefore, the subsequent post-regulator LDO must have good power supply rejection (PSR) up to switching frequencies of SMPS. Unfortunately, the conventional LDOs have poor PSR at high frequencies. The objective of this research is to develop novel LDO regulators that can achieve good high frequency PSR performance. In this thesis, two PSR improvement methods are presented. The first method proposes a novel power supply noise-cancelling scheme to improve the PSR of an external-capacitor LDO. The proposed power supply noise-cancelling scheme is designed using adaptive power consumption, thereby not degrading the power efficiency of the LDO. The second method proposes a feed forward ripple cancellation technique to improve the PSR of capacitor-less LDO; also a dynamically powered transient improvement scheme has been proposed. The feed forward ripple cancellation is designed by reusing the load transient improvement block, thus achieving the improvement in PSR with no additional power consumption. Both the projects have been designed in TSMC 0.18 μm technology. The first method achieves a PSR of 66 dB up to 1 MHz where as the second method achieves a 55 dB PSR up to 1 MHz

Conception d'un réseau de plots configurables multifonctions analogiques et numériques combiné à un réseau de distribution de puissance intégrés à l'échelle de la tranche de silicium

RÉSUMÉ De nos jours, les systèmes électroniques sont en constante croissance en taille et en complexité. Cette complexité combinée à la réduction du temps de mise en marché rendant le design de systèmes électroniques un grand défi pour les designers. Une plateforme de prototypage a récemment été introduite afin de s’attaquer toutes ces contraintes à la fois. Cette plateforme s’appuie sur l’implémentation d’un circuit configurable à l’échelle d’une tranche de silicium complète de 200mm de diamètre. Cette surface est recouverte d’une mer de plots conducteurs configurables appelés NanoPads. Ces NanoPads sont suffisamment petits pour supporter des billes d’un diamètre de 250 μm et d’un espacement de 500 μm et sont regroupés en matrices de 4×4 pour former des Cellules, qui sont à leur tour assemblées en Réticules de 32×32. Ces Réticules sont ensuite photo-répétés sur toute la surface d’une tranche de silicium et sont interconnectés entre eux pour former le WaferIC. Cet arrangement particulier de plots conducteurs configurables permet à un usager de déposer sur la surface active du WaferIC les circuits intégrés constituant un système électronique, sans tenir en compte l’orientation spatiale de ces derniers, de créer un schéma d’interconnexions, de distribution la puissance et de débuter le prototypage du système en question. Une version préliminaire a été fabriquées et testées avec succès et permet d’alimenter des circuits -intégrés et de configurer le WaferIC pour les interconnecter. Cette thèse par articles présente une nouvelle version du WaferIC avec une nouvelle proposition de distribution de la puissance avec une approche de maîtres-esclaves qui met en valeur l’utilisation de plusieurs rails d’alimentation afin d’améliorer le rendement énergétique. Il est également mis de l’avant un réseau très dense de convertisseurs analogique-numérique (CAN) et numérique-analogique (CNA) de plus de 300k éléments, tolérant aux défectuosités et aux défauts de fabrication. Ce réseau de CAN-CNA permet d’améliorer le WaferIC avec la transmission de signaux analogiques, en plus des signaux numériques. Ce manuscrit comporte trois articles : un publié chez « Springer Science & Business Media Analog Integrated Circuits and Signal Processing », un publié chez « IEEE Transactions on Circuits and Systems I : Regular Papers » et finalement un soumis chez « IEEE Transactions on Very Large Scale Integration ».----------ABSTRACT Nowadays, electronic systems are in constant growth, size and complexity; combined with time to market it makes a challenge for electronic system designers. A prototyping platform has been recently introduced and addresses all those constraints at once. This platform is based on an active 200 mm in diameter wafer-scale circuit, which is covered with a set of small configurable and conductive pads called NanoPads. These NanoPads are designed to be small enough to support any integrated-circuit μball of a 250 μm diameter and 500 μm of pitch. They are assembled in a 4×4 matrix, forming a Unit-Cell, which are grouped in a Reticle-Image of 32×32. These Reticle-Images are photo-repeated over the entire surface of a 200 mm in diameter wafer and are interconnected together using interreticle stitching. This active wafer-scale circuit is called a WaferIC. This particular topology and distribution of NanoPads allows an electronic system designer to manually deposit any integrated-circuit (IC) on the active alignment insensitive surface of the WaferIC, to build the netlist linking all the ICs, power-up the systems and start the prototyping of the system. In this manuscript-based thesis, we present an improved version of the WaferIC with a novel approach for the power distribution network with a master-slave topology, which makes the use of embedded dual-power-rail voltage regulators in order to improve the power efficiency and decrease thermal dissipation. We also propose a default-tolerant network of analog to digital (ADC) and digital to analog (DAC) converters of more than 300k. This ADC-DAC network allows the WaferIC to not only support digital ICs but also propagate analog signals from one NanoPad to another. This thesis includes 3 papers : one submission to "Springer Science & Business Media Analog Integrated Circuits and Signal Processing", one submission to "IEEE Transactions on Circuits and Systems I : Regular Papers" and finally one submission to "IEEE Transactions on Very Large-Scale Integration". These papers propose novel architectures of dualrail voltage regulators, configurable analog buffers and configurable voltage references, which can be used as a DAC. A novel approach for a power distribution network and the integration of all the presented architectures is also proposed with the fabrication of a testchip in CMOS 0.18 μm technology, which is a small-scale version of the WaferIC

Low Power DC-DC Converters and a Low Quiescent Power High PSRR Class-D Audio Amplifier

High-performance DC-DC voltage converters and high-efficient class-D audio amplifiers are required to extend battery life and reduce cost in portable electronics. This dissertation focuses on new system architectures and design techniques to reduce area and minimize quiescent power while achieving high performance. Experimental results from prototype circuits to verify theory are shown. Firstly, basics on low drop-out (LDO) voltage regulators are provided. Demand for system-on-chip solutions has increased the interest in LDO voltage regulators that do not require a bulky off-chip capacitor to achieve stability, also called capacitor- less LDO (CL-LDO) regulators. Several architectures have been proposed; however, comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This dissertation compares CL-LDOs in a unified manner. Five CL-LDO regulator topologies were designed, fabricated, and tested under common design conditions. Secondly, fundamentals on DC-DC buck converters are presented and area reduction techniques for the external output filter, power stage, and compensator are proposed. A fully integrated buck converter using standard CMOS technology is presented. The external output filter has been fully-integrated by increasing the switching frequency up to 45 MHz. Moreover, a monolithic single-input dual-output buck converter is proposed. This architecture implements only three switches instead of the four switches used in conventional solutions, thus potentially reducing area in the power stage through proper design of the power switches. Lastly, a monolithic PWM voltage mode buck converter with compact Type-III compensation is proposed. This compensation scheme employs a combination of Gm-RC and Active-RC techniques to reduce the area of the compensator, while maintaining low quiescent power consumption and fast transient response. The proposed compensator reduces area by more than 45% when compared to an equivalent conventional Type-III compensator. Finally, basics on class-D audio amplifiers are presented and a clock-free current controlled class-D audio amplifier using integral sliding mode control is proposed. The proposed amplifier achieves up to 82 dB of power supply rejection ratio and a total harmonic distortion plus noise as low as 0.02%. The IC prototype’s controller consumes 30% less power than those featured in recently published works