Implementation Of Modular Testing In Bios Development And Debug

This project presents a modular approach in BIOS development in purpose to tackle the problem of long development time with the existing methodologies which are hardware platform approach and virtual platform approach. The proposed approach consists of previous generation platform, a FPGA card and UEFI drivers. The FPGA is loaded with the RTL of one Intellectual Property (IP) from the current company project. The chosen IP is Low Power Subsystem (LPSS). The card is then plugged into the PCI slot of the platform. Besides, UEFI Configuration Driver and UEFI Reset Driver are built to configure and reset the LPSS registers respectively. Both of them are stored into a thumb drive and plugged into USB port of the platform. They are executed in the UEFI Shell environment. In this project, the development time of LPSS needed by the three methodologies which are hardware platform approach, virtual platform approach and modular approach are compared. The results indicate that modular approach is capable to save up to 90% of the development time in comparison with the other two approaches. At the same time, both of the UEFI drivers are functioning correctly. The processing time of both of the UEFI Configuration Driver and UEFI Reset Driver are about 1 to 2 seconds only. In conclusion, the novelty of the modular approach is that the BIOS can be developed in modular basis, without having to develop the BIOS as a whole. Therefore, it is able to cut down the BIOS development time efficientl

Investigating SRAM PUFs in large CPUs and GPUs

Physically unclonable functions (PUFs) provide data that can be used for cryptographic purposes: on the one hand randomness for the initialization of random-number generators; on the other hand individual fingerprints for unique identification of specific hardware components. However, today's off-the-shelf personal computers advertise randomness and individual fingerprints only in the form of additional or dedicated hardware. This paper introduces a new set of tools to investigate whether intrinsic PUFs can be found in PC components that are not advertised as containing PUFs. In particular, this paper investigates AMD64 CPU registers as potential PUF sources in the operating-system kernel, the bootloader, and the system BIOS; investigates the CPU cache in the early boot stages; and investigates shared memory on Nvidia GPUs. This investigation found non-random non-fingerprinting behavior in several components but revealed usable PUFs in Nvidia GPUs.Comment: 25 pages, 6 figures. Code in appendi

IoT single board computer to replace a home server

Home servers are popular among computer enthusiasts for hosting various applications, including Linux OS with web servers, database solutions, and private cloud services, as well as for VPN, torrent, file-sharing, and streaming. Single Board Computers (SBCs), once used for small projects, have now evolved and can be used to control multiple devices in the IoT space. SBCs have become more powerful and can run many of the same applications as traditional home servers. In light of the energy crisis, this study will examine the feasibility of replacing a conventional home server with an SBC while maintaining service quality and evaluating performance and availability. The power consumption of both solutions will be compared.info:eu-repo/semantics/publishedVersio

Accelerating BLAST Computation on an FPGA-enhanced PC Cluster

This paper introduces an FPGA-based scheme to accelerate mpiBLAST, which is a parallel sequence alignment algorithm for computational biology. Recent rapidly growing biological databases for sequence alignment require highthroughput storage and network rather than computing speed. Our scheme utilizes a specialized hardware configured on an FPGA-board which connects flash storage and other FPGAboards directly. The specialized hardware configured on the FPGAs, we call a Data Stream Processing Engine (DSPE), take a role for preprocessing to adjust data for high-performance multi- and many- core processors simultaneously with offloading system-calls for storage access and networking. DSPE along the datapath achieves in-datapath computing which applies operations for data streams passing through the FPGA. Two functions in mpiBLAST are implemented using DSPE to offload operations along the datapath. The first function is database partitioning, which distributes the biological database to multiple computing nodes before commencing the BLAST processes. Using DSPE, we observe a 20-fold improvement in computation time for the database partitioning operation. The second function is an early part of the BLAST process that determines the positions of sequences for more detailed computations. We implement IDP-BLAST (In-datapath BLAST), which annotates positions in data streams from solid-state drives. We show that IDP-BLAST accelerates the computation time of the preprocess of BLAST by a factor of three hundred by offloading heavy operations to the introduced special hardware