Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis

The reversible logic gates are used to improve the power dissipation in modern computer applications. The floating-point numbers with reversible features are added advantage to performing complex algorithms with high-performance computations. This manuscript implements an efficient reversible floating-point arithmetic (RFPA) unit, and its performance metrics are realized in detail. The RFP adder/subtractor (A/S), RFP multiplier, and RFP divider units are designed as a part of the RFP arithmetic unit. The RFPA unit is designed by considering basic reversible gates. The mantissa part of the RFP multiplier is created using a 24x24 Wallace tree multiplier. In contrast, the reciprocal unit of the RFP divider is designed using Newton Raphson’s method. The RFPA unit and its submodules are executed in parallel by utilizing one clock cycle individually. The RFPA unit and its submodules are synthesized separately on the Vivado IDE environment and obtained the implementation results on Artix-7 field programmable gate array (FPGA). The RFPA unit utilizes only 18.44% slice look-up tables (LUTs) by consuming the 0.891 W total power on Artix-7 FPGA. The RFPA unit sub-models are compared with existing approaches with better performance metrics and chip resource utilization improvements

RESOURCE EFFICIENT DESIGN OF QUANTUM CIRCUITS FOR CRYPTANALYSIS AND SCIENTIFIC COMPUTING APPLICATIONS

Quantum computers offer the potential to extend our abilities to tackle computational problems in fields such as number theory, encryption, search and scientific computation. Up to a superpolynomial speedup has been reported for quantum algorithms in these areas. Motivated by the promise of faster computations, the development of quantum machines has caught the attention of both academics and industry researchers. Quantum machines are now at sizes where implementations of quantum algorithms or their components are now becoming possible. In order to implement quantum algorithms on quantum machines, resource efficient circuits and functional blocks must be designed. In this work, we propose quantum circuits for Galois and integer arithmetic. These quantum circuits are necessary building blocks to realize quantum algorithms. The design of resource efficient quantum circuits requires the designer takes into account the gate cost, quantum bit (qubit) cost, depth and garbage outputs of a quantum circuit. Existing quantum machines do not have many qubits meaning that circuits with high qubit cost cannot be implemented. In addition, quantum circuits are more prone to errors and garbage output removal adds to overall cost. As more gates are used, a quantum circuit sees an increased rate of failure. Failures and error rates can be countered by using quantum error correcting codes and fault tolerant implementations of universal gate sets (such as Clifford+T gates). However, Clifford+T gates are costly to implement with the T gate being significantly more costly than the Clifford gates. As a result, designers working with Clifford+T gates seek to minimize the number of T gates (T-count) and the depth of T gates (T-depth). In this work, we propose quantum circuits for Galois and integer arithmetic with lower T-count, T-depth and qubit cost than existing work. This work presents novel quantum circuits for squaring and exponentiation over binary extension fields (Galois fields of form GF(2 m )). The proposed circuits are shown to have lower depth, qubit and gate cost to existing work. We also present quantum circuits for the core operations of multiplication and division which enjoy lower T-count, T-depth and qubit costs compared to existing work. This work also illustrates the design of a T-count and qubit cost efficient design for the square root. This work concludes with an illustration of how the arithmetic circuits can be combined into a functional block to implement quantum image processing algorithms

Hardware-Based Sobel Gradient Computations for Sharpness Enhancement

The majority of imaging systems are software based; they require some kind of microprocessor or microcontroller for the imaging algorithms to run. As the speed requirements of imaging and communications systems increase, the need for more hardware-based imaging systems arises. These fully hardware systems solve the fundamental problem inherent in software-based solutions, in which the speed of the algorithms depend on the instruction cycle speed of the processor. Once an algorithm is designed directly on hardware, the speed of the algorithm depends on the system clock frequency and the propagation delays of the logic cells (or standard cells) used in the design, usually measured in nanoseconds per cell. Therefore, such systems no longer depend on any instruction cycle delays, as there is no microprocessor involved. Most modern imaging and communications systems rely on digital signal processing (DSP) to compute complex mathematical operations. The emergence of powerful and low-cost field-programmable gate array (FPGA) devices with hundreds of arithmetic multipliers has enabled the development of many such DSP hardware applications, traditionally implemented only as software solutions

Implemetasi Komputasi Akar Kuadrat Resolusi Tinggi pada Field Programmable Gate Array (FPGA)

Komputasi akar kuadrat diperlukan pada beberapa proses pengendalian, diantaranya untuk Direct Torque Control (DTC) pada sistem penggerak motor yang membutuhkan proses perhitungan yang sangat cepat. Field Programmable Gate Array (FPGA) merupakan salah satu perangkat yang dapat digunakan untuk implementasi komputasi yang memerlukan kecepatan dan presisi tinggi. Penerapan komputasi akar kuadrat pada FPGA menggunakan metode digit by digit non-restoring dengan beberapa modifikasi agar memiliki hasil perhitungan dengan nilai error yang kecil. Sistem tersebut diimplementasikan menggunakan 32-bit input dan 16-bit output. Proses perhitungan melibatkan Finite State machine (FSM) untuk menghemat resource yang diperlukan. Proses verifikasi sistem dilakukan dalam dua tahap, yaitu verifikasi fungsional dengan aplikasi ModelSim-Altera dan verifikasi hardware menggunakan modul FPGA Cylcone IV EP4CE6E228N. Hasil verifikasi menunjukkan bahwa hasil perhitungan akar kuadrat memiliki resolusi sampai dengan 0,0039. Selain itu, sistem ini membutuhkan 157 Logic Elements dan 120 register dengan kecepatan clock tertinggi yang dicapainya adalah 205 MHz untuk input 32 bit AbstractSquare root computing is required in several control processes, such as for Direct Torque Control (DTC) on motor drive systems that require a very fast calculation process. Field Programmable Gate Array (FPGA) is one of the devices that recommended for high speed and precision computation. The implementation of the square root on the FPGA uses the digit-by-digit non-restoring method with some modifications to get a high precision of computation result. The system is implemented using 32-bit input and 16-bit output. The calculation process involves a Finite State machine (FSM) to minimize computation resources. The system verification process is carried out in two stages, i.e. functional verification using the ModelSim-Altera and hardware verification using the FPGA Cylcone IV EP4CE6E228N. The verification shows that the result of the square root calculation has a resolution of up to 0.0039. In addition, the system requires 157 Logic Elements and 120 registers with the highest clock speed can achieves 205 MHz for 32-bit input

Characterization of MEMS Electrostatic Actuators Beyond Pull-In

The operational range of MEMS electrostatic parallel plate actuators can be extended beyond pull-in with the presence of an intermediate dielectric layer, which has a significant effect on the behaviour of such actuators. Here we study the behaviour of cantilever beam electrostatic actuators beyond pull-in using a beam model along with a dielectric layer. Three possible static configurations of the beam are identified over the operational voltage range. We call them floating, pinned and flat: the latter two are also called arc-type and S-type in the literature. We compute the voltage ranges over which the three configurations can exist, and the points where transitions occur between these configurations. Voltage ranges are identified where bi-stable and tri-stable states exist. A classification of all possible transitions (pull-in and pull-out as well as transitions we term pull-down and pull-up) is presented based on the dielectric layer parameters. A scaling law is found in the flat configuration. Dynamic stability analyses are presented for the floating and pinned configurations. For high dielectric layer thickness, discontinuous transitions between configurations disappear and the actuator has smooth predictable behaviour, but at the expense of lower tunability. Hence, designs with variable dielectric layer thickness can be studied in future to obtain both regularity/predictability as well as high tunability

Reliable and Fault-Resilient Schemes for Efficient Radix-4 Complex Division

Complex division is commonly used in various applications in signal processing and control theory including astronomy and nonlinear RF measurements. Nevertheless, unless reliability and assurance are embedded into the architectures of such structures, the suboptimal (and thus erroneous) results could undermine the objectives of such applications. As such, in this thesis, we present schemes to provide complex number division architectures based on (Sweeney, Robertson, and Tocher) SRT-division with fault diagnosis mechanisms. Different fault resilient architectures are proposed in this thesis which can be tailored based on the eventual objectives of the designs in terms of area and time requirements, among which we pinpoint carefully the schemes based on recomputing with shifted operands (RESO) to be able to detect both natural and malicious faults and with proper modification achieve high throughputs. The design also implements a minimized look up table approach which favors in error detection based designs and provides high fault coverage with relatively-low overhead. Additionally, to benchmark the effectiveness of the proposed schemes, extensive fault diagnosis assessments are performed for the proposed designs through fault simulations and FPGA implementations; the design is implemented on Xilinx Spartan-VI and Xilinx Virtex-VI FPGA families

Quantum Attacks on Mersenne Number Cryptosystems

Mersenne number based cryptography was introduced by Aggarwal et al. as a potential post- quantum cryptosystem in 2017. Shortly after the publication Beunardeau et al. propose a lattice based attack significantly reducing the security margins. During the NIST post-quantum project Aggarwal et al. and Szepieniec introduced a new form of Mersenne number based cryptosystems which remain secure in the presence of the lattice reduction attack. The cryptoschemes make use of error correcting codes and have a low but non-zero probability of failure during the decoding phase. In the event of a decoding failure information about the secret key may be leaked and may allow for new attacks. In the first part of this work, we analyze the Mersenne number cryptosystem and NIST submission Ramstake and identify approaches to exploit the information leaked by decoding failures. We describe different attacks on a weakened variant of Ramstake. Furthermore we pair the decoding failures with a timing attack on the code from the submission package. Both our attacks significantly reduce the security margins compared to the best known generic attack. However, our results on the weakened variant do not seem to carry over to the unweakened cryptosystem. It remains an open question whether the information flow from decoding failures can be exploited to break Ramstake. In the second part of this work we analyze the Groverization of the lattice reduction attack by Beunardeau et al.. The incorporation of classical search problem into a quantum framework promises a quadratic speedup potentially reducing the security margin by half. We give an explicit description of the quantum circuits resulting from the translation of the classical attack. This description contains, to the best of our knowledge, the first in depth description and analysis of a quantum variant of the LLL algorithm. We show that the Groverized attack requires a large (but polynomial) overhead of quantum memory

Experimental and Theoretical Brownian Dynamics Analysis of Ion Transport During Cellular Electroporation of E. coli Bacteria

Escherichia coli bacterium is a rod-shaped organism composed of a complex double membrane structure. Knowledge of electric field driven ion transport through both membranes and the evolution of their induced permeabilization has important applications in biomedical engineering, delivery of genes and antibacterial agents. However, few studies have been conducted on Gram-negative bacteria in this regard considering the contribution of all ion types. To address this gap in knowledge, we have developed a deterministic and stochastic Brownian dynamics model to simulate in 3D space the motion of ions through pores formed in the plasma membranes of E. coli cells during electroporation. The diffusion coefficient, mobility, and translation time of Ca$^{2+}$, Mg$^{2+}$, Na$^+$, K$^+$, and Cl$^-$ ions within the pore region are estimated from the numerical model. Calculations of pore's conductance have been validated with experiments conducted at Gustave Roussy. From the simulations, it was found that the main driving force of ionic uptake during the pulse is the one due to the externally applied electric field. The results from this work provide a better understanding of ion transport during electroporation, aiding in the design of electrical pulses for maximizing ion throughput, primarily for application in cancer treatment.Comment: Annals of Biomedical Engineering, 202

Numerical Modeling and Experimental Testing of a Pendulum Wave Energy Converter (PeWEC)

The research activities described in the present work aims to develop a pendulum converter (PeWEC: Pendulum Wave Energy Converter) for the Mediterranean Sea, where waves are shorter, thus with a higher frequency. In particular, the Pantelleria Island site wave climate is assumed as reference. The research activities started from the preliminary investigation of the working principle validity in the case of the Mediterranean Sea wave characteristics, taking into account a 1:45 scale prototype. The numerical model reliability and the success of experimental tests motivated the design and development of a 1:12 scaled device, useful for a deeper investigation of the technology capabilities and performances. Globally, the technology readiness level (TRL) was increased from 1 to 4. Important effort were focused in the development of a reliable model-based design and optimization methodology for the investigation of a full scale configuration. The latter was widely used to identify a preliminary full scale configuration and to assess the economic viability of the PeWEC technology in the Mediterranean Sea context. Results were benchmarked against the ISWEC pilot plant, deployed in 2015, in Pantelleria Island. One of the major outcomes of this analysis is a detailed overview of the advantages and drawbacks of an active (ISWEC) and a passive (PeWEC) technology, together with some guidelines for the improvement of this technology