Stabilized high-power laser system for the gravitational wave detector advanced LIGO

An ultra-stable, high-power cw Nd:YAG laser system, developed for the ground-based gravitational wave detector Advanced LIGO (Laser Interferometer Gravitational-Wave Observatory), was comprehensively characterized. Laser power, frequency, beam pointing and beam quality were simultaneously stabilized using different active and passive schemes. The output beam, the performance of the stabilization, and the cross-coupling between different stabilization feedback control loops were characterized and found to fulfill most design requirements. The employed stabilization schemes and the achieved performance are of relevance to many high-precision optical experiments

GPS Carrier Tracking Loop Performance in the presence of Ionospheric Scintillations

The performance of several GPS carrier tracking loops is evaluated using wideband GPS data recorded during strong ionospheric scintillations. The aim of this study is to determine the loop structures and parameters that enable good phase tracking during the power fades and phase dynamics induced by scintillations. Constant-bandwidth and variable-bandwidth loops are studied using theoretical models, simulation, and tests with actual GPS signals. Constant-bandwidth loops with loop bandwidths near 15 Hz are shown to lose phase lock during scintillations. Use of the decision-directed discriminator reduces the carrier lock threshold by ∼1 dB relative to the arctangent and conventional Costas discriminators. A proposed variablebandwidth loop based on a Kalman filter reduces the carrier lock threshold by more than 7 dB compared to a 15-Hz constant-bandwidth loop. The Kalman filter-based strategy employs a soft-decision discriminator, explicitly models the effects of receiver clock noise, and optimally adapts the loop bandwidth to the carrier-to-noise ratio. In extensive simulation and in tests using actual wideband GPS data, the Kalman filter PLL demonstrates improved cycle slip immunity relative to constant bandwidth PLLs.Aerospace Engineering and Engineering Mechanic

Design and Analysis of an Efficient Phase Locked Loop for Fast Phase and Frequency Acquisition

The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high-performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time. PLL is a mixed signal circuit as its architecture involves both digital and analog signal processing units. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in CADENCE Virtuoso Analog Design Environment. Here a current starved ring oscillator has been considered for its superior performance in form of its low chip area, low power consumption and wide tuneable frequency range. The layout structure of the PLL is drawn in CADENCE VirtuosoXL Layout editor. Different types of simulations are carried out in the Spectre simulator. The pre and post layout simulation results of PLL are reported in this work. It is found that the designed PLL consumes 11.68mW power from a 1.8V D.C. supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) is the heart of the PLL, so the optimization of the VCO circuit is also carried out using the convex optimization technique. The results of the VCO designed using the convex optimization method is compared with traditional method

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

High dynamic global positioning system receiver

A Global Positioning System (GPS) receiver having a number of channels, receives an aggregate of pseudorange code time division modulated signals. The aggregate is converted to baseband and then to digital form for separate processing in the separate channels. A fast fourier transform processor computes the signal energy as a function of Doppler frequency for each correlation lag, and a range and frequency estimator computes estimates of pseudorange, and frequency. Raw estimates from all channels are used to estimate receiver position, velocity, clock offset and clock rate offset in a conventional navigation and control unit, and based on the unit that computes smoothed estimates for the next measurement interval

Digital phase-lock loop having an estimator and predictor of error

A digital phase-lock loop (DPLL) which generates a signal with a phase that approximates the phase of a received signal with a linear estimator. The effect of a complication associated with non-zero transport delays related to DPLL mechanization is then compensated by a predictor. The estimator provides recursive estimates of phase, frequency, and higher order derivatives, while the predictor compensates for transport lag inherent in the loop

A functional description of the advanced receiver

The breadboard Advanced Receiver 2 (ARX 2) that is currently being built for future use in NASA's Deep Space Network (DSN) is described. The hybrid analog/digital receiver performs multiple functions including carrier, subcarrier, and symbol synchronization. Tracking can be achieved for residual, suppressed, or hybrid carriers and for both sinusoidal and square-wave subcarriers. Other functions such as time-tagged Doppler extraction and monitor/control are also discussed, including acquisition algorithms and lock-detection schemes. System requirements are specified and a functional description of the ARX 2 is presented. The various digital signal-processing algorithms used are also discussed and illustrated with block diagrams