Aerospace Applications of Microprocessors

An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed

Neural network computing using on-chip accelerators

The use of neural networks, machine learning, or artificial intelligence, in its broadest and most controversial sense, has been a tumultuous journey involving three distinct hype cycles and a history dating back to the 1960s. Resurgent, enthusiastic interest in machine learning and its applications bolsters the case for machine learning as a fundamental computational kernel. Furthermore, researchers have demonstrated that machine learning can be utilized as an auxiliary component of applications to enhance or enable new types of computation such as approximate computing or automatic parallelization. In our view, machine learning becomes not the underlying application, but a ubiquitous component of applications. This view necessitates a different approach towards the deployment of machine learning computation that spans not only hardware design of accelerator architectures, but also user and supervisor software to enable the safe, simultaneous use of machine learning accelerator resources. In this dissertation, we propose a multi-transaction model of neural network computation to meet the needs of future machine learning applications. We demonstrate that this model, encompassing a decoupled backend accelerator for inference and learning from hardware and software for managing neural network transactions can be achieved with low overhead and integrated with a modern RISC-V microprocessor. Our extensions span user and supervisor software and data structures and, coupled with our hardware, enable multiple transactions from different address spaces to execute simultaneously, yet safely. Together, our system demonstrates the utility of a multi-transaction model to increase energy efficiency improvements and improve overall accelerator throughput for machine learning applications

The end of the Intel age

Thesis (S.M. in Engineering and Management)--Massachusetts Institute of Technology, Engineering Systems Division, System Design and Management Program, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 108-111).Executive Summary - The End of the Intel Era. Today, Intel is nearly synonymous with computers. In the past thirty years nearly all personal computers and the great majority of servers have shipped with a processor based on Intel's x86 architecture, of which Intel is the dominant vendor. Yet the past few years have seen a subtle yet remarkable convergence of different industry trends that very well may topple the semiconductor giant. For the past three decades, computers have largely assumed the same shape and form, regardless of their task. Laptops, desktops, and servers have all been based on the same open modular architecture established by IBM. Yet this is not likely to be the case going forward. The past decade has seen the rise of embedded computing, perhaps best epitomized by smartphones and tablet computers. Instead of the standard PC architecture where individual components can be easily exchanged, embedded devices are typically modular designs with highly integrated physical components. Independent functional units, all designed by independent companies, are integrated onto the same piece of silicon to achieve system cost and performance targets. Instead of a standard x86 processor, each device category likely has a chip optimized for its specific application. At the same time that the form of computing is changing, we are witnessing a redistribution of where computing power resides with Cloud Computing and data centers. These have ordinarily been the province of Intel based machines, but data centers have moved from using standard off-the-shelf PCs to custom designed motherboards. Again, we are seeing a shift from the modular personal computer architecture to one that is customized for the task at hand. Another concern for Intel is that the standard metrics by which products compete are in flux. For both embedded systems and data centers, the operational costs and constraints are starting to outweigh the initial outlay costs. An example is the industry shift from overall performance to system power efficiency. Intel has been a relentless driver of processor performance, and this is a significant change of focus for its R&D divisions. Of all Intel's competitors, ARM best represents the magnitude of these challenges for Intel, and is well positioned to take advantage of all these trends. Their business model of licensing their design is well suited for a world with customized architectures, and their extensive experience in low power embedded devices has given them an advantage over Intel in processor power efficiency. Intel is heavily invested in its existing vision of the market. They have always maintained a manufacturing process advantage through tremendous investments in new foundries, and have long championed the open PC modular architecture. Time will ultimately show if Intel is capable of meeting these growing challenges. Yet it is clear that in order to do so, it must make radical changes to itself. One may ask if it is even the same company that emerges.by Robert Swope Fleming.S.M.in Engineering and Managemen

Mixing multi-core CPUs and GPUs for scientific simulation software

Recent technological and economic developments have led to widespread availability of multi-core CPUs and specialist accelerator processors such as graphical processing units (GPUs). The accelerated computational performance possible from these devices can be very high for some applications paradigms. Software languages and systems such as NVIDIA's CUDA and Khronos consortium's open compute language (OpenCL) support a number of individual parallel application programming paradigms. To scale up the performance of some complex systems simulations, a hybrid of multi-core CPUs for coarse-grained parallelism and very many core GPUs for data parallelism is necessary. We describe our use of hybrid applica- tions using threading approaches and multi-core CPUs to control independent GPU devices. We present speed-up data and discuss multi-threading software issues for the applications level programmer and o er some suggested areas for language development and integration between coarse-grained and ne-grained multi-thread systems. We discuss results from three common simulation algorithmic areas including: partial di erential equations; graph cluster metric calculations and random number generation. We report on programming experiences and selected performance for these algorithms on: single and multiple GPUs; multi-core CPUs; a CellBE; and using OpenCL. We discuss programmer usability issues and the outlook and trends in multi-core programming for scienti c applications developers

Android on x86

Computer scienc

Development of PCI Embedded Card Useful for Microcontroller Trainer

Not availabl

An intelligent magnetic tape controller

This thesis describes a system to allow a mass storage device to be installed in a position remote from the computer system which controls it. This system is intended to allow undergraduate students in the Electrical Engineering department at UCT to make use of two nine channel tape drives installed in the undergraduate interfaced to accessed by laboratory for project work. The drives are the department's PDP-11/23 computer, and may be standard operating system directives, as the controller simulates a conventional computer peripheral. The system consists of an SA-Bus based tape transport controller which interfaces to the host computer system via a serial line. The following hardware was designed and built specifically for this system : 1. A CPU card based on the in Tel 80188 microprocessor, incorporating high speed DMA (direct memory access) channels and two interrupt driven serial lines. 2. A timing and control module for the tape transports. This consists of two SA-Bus cards. Two sets of software were written for the system. These are the following : 1. Software to operate the tape controller. This consists of six modules written in Pascal-86 and 8086 assemblers. 2. Software to allow the PDP-11/23 to control the tape drives. This is in the. form of an RSX-11 device driver written in PDP-11 assembler. To allow the particular to proposed local system allow area highly modular form. to be easily the system to network) , the upgraded in the future (in be incorporated into UCT's software was written in an addition to being controlled by a host system in remote mode the tape controller also has the ability to perform a variety of operations in local mode. These include the ability to copy and erase tapes, as well as a comprehensive set of diagnostic functions. When in local operations mode the controller is menu driven, making its use by persons who are not familiar with it quick and easy

A competitive analysis of the personal computer industry

Thesis (M.S.)--Massachusetts Institute of Technology, Alfred P. Sloan School of Management, 1982.MICROFICHE COPY AVAILABLE IN ARCHIVES AND DEWEYBibliography: leaves 188-192.by Gary Noble Farner.M.S

Training platform for the design of a windows multimedia device

There are many Windows Multimedia plug-in cards available for a Personal Computer (PC), but they are not suitable for a laboratory teaching platform for several reasons. Firstly, their hardware and software details are not available because of the market driven need to keep all hardware and software details from competitors. Secondly, the cards are not designed to allow faults to be introduced. Thirdly there is the inherent requirement that Windows applications be uniform to the point where application software sees the same interface, irrespective o f which Windows compatible card is being used. These latter points are highly desirable from the user's point of view but not from a teaching viewpoint, where the goal is to enlighten the student in the hardware and software design techniques used to perform the stated objective. The Multimedia Teaching Platform consists of a sound card, Windows 3.1 application and a Windows standard mode device driver. The sound card can continuously play or record audio files to the PC's hard disc in an analogue or a digital format. The digital format conforms to the consumer digital formats, IEC-958 Consumer, S/PDIF and CP-340 Type 2. Programmable logic was used on the sound card to allow hardware faults to be easily introduced. Hardware faults can be introduced by replacing the memory device which programs the logic array. Software design faults can be introduced by providing faulty source code for the device drivers and for the user interface. By introducing both hardware and software design faults, students can gain valuable experience in software and hardware debugging techniques and in the Windows environment