Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Module wireless 60 GHz intégré en 3D sur silicium

The evolution of semi-conductor technology nodes has led to a significant miniaturization of today's RF front-ends and to the enhancement of the electrical performance of transceivers at higher frequencies. This leads to the diversification of RF/millimeter-wave (30 – 300 GHz) applications in the fields of telecommunications, multimedia entertainment, automotive and security. More specifically, telecommunications are going through a real revolution with the creation of new standards (such as WiGiG and IEEE 802.11ad) and the introduction of new network architectures based on point-to-point links as the backbone of the 5th generation of mobile networks. In this PhD work, we will focus on integrated wireless and low consumption modules operating in the 57 – 66 GHz band (generally designated as the 60 GHz band). At these frequencies, the free-space wavelength is comparable to the characteristic dimensions of most standard transceiver packages. This opens an opportunity to integrate the antennas as well as other passive components directly to the metal/dielectric stack or in the package. This new generation of electronic devices which are dedicated to the nomad terminal market brings new challenges in terms of electrical performance, mechanical reliability, cost and manufacturability. Microelectronic packaging plays in this case a key role in defining the global performance of the system. Its functions extend beyond the protection of the IC and cover other schemes with opportunities to integrate passive and active devices. This work focuses on the study of an SiP module (System-in-Package) featuring 3D integration on Silicon interposer. The dissertation comprises four chapters and is structured as follows: In the first chapter, a brief introduction of millimeter-waves and their propagation conditions is given. Then, examples of current and emerging civilian and military applications are addressed. State of the art of SiP/mmW modules is then presented according to different technology approaches proposed by industrial and academic contributors. The second chapter is dedicated to the study of a 60 GHz integrated module on a high-resistivity silicon interposer chip. We focus on electrical characterization methods which are adapted to different building blocks of the silicon back-end technology. These include interconnects, dielectrics and integrated antennas. The characterization steps also include full-scale and standard-compliant tests of two communicating 60 GHz modules. In the third chapter, we propose to improve the existing module with a novel antenna design based on a High-Impedance Surface (HIS) reflector. This design is intended to bring more compactness and higher reliability to the original one while conserving the overall electrical performance. Finally, the fourth chapter deals with the fabrications and experimental validation of the antenna test vehicle as well as the wideband characterization of the dielectrics used for the new stack.L'évolution des nœuds technologiques dans l'industrie des semi-conducteurs se traduit de nos jours, dans le domaine des radiofréquences, par une miniaturisation des front-ends et une amélioration des performances électriques des émetteurs-récepteurs à des fréquences de plus en plus hautes. Cette évolution a conduit à la diversification des applications en bandes millimétriques (30 – 300 GHz) dans les secteurs des télécommunications, du divertissement multimédia, de l'automobile et de la sécurité. Plus particulièrement, le secteur des télécommunications connaît aujourd'hui une réelle révolution avec la création de nouveaux standards pour les liens sans-fil millimétriques à courte portée (comme WiGiG et IEEE 802.11ad) et l'apparition de nouvelles architectures basées sur des liaisons point-à-point qui constitueront dans les prochaines années la colonne vertébrale de la cinquième génération des réseaux mobiles. Dans le cadre de ces travaux de thèse, un intérêt particulier sera porté sur les modules intégrés sans fils et à faible consommation opérant dans la bande 57 – 66 GHz (dite généralement 60 GHz). A ces fréquences, la longueur d'onde en espace libre est comparable aux dimensions caractéristiques des boitiers standards utilisés pour l'encapsulation des transceivers. Il devient donc envisageable d'intégrer les antennes ainsi que d'autres composants passifs directement dans l'empilement technologique du circuit ou dans le boitier. Cette nouvelle génération de dispositifs électroniques, destinés au marché des terminaux portables, introduit de nouveaux défis en termes de performances électriques, de fiabilité mécanique, de coût et de possibilités d'industrialisation. Le packaging microélectronique joue dans ce cas un rôle principal dans la définition des performances globales du système qui s'étend au-delà de la simple protection de circuits intégrés pour couvrir d'autres fonctions d'intégration de divers dispositifs actifs et passifs. L'axe principal d'étude adopté ici porte sur le packaging d'un module SiP (System-in-Package) intégré en 3D et réalisé en technologie interposer silicium. Le mémoire de thèse s'articule en quatre chapitres : Le premier chapitre donne dans un premier temps une brève introduction aux bandes millimétriques et aux conditions de propagation spécifiques à ces bandes avant de présenter des exemples d'applications relevant de divers domaines civils et militaires. Ensuite, nous dressons un état de l'art des modules SiP millimétriques intégrés selon différentes approches technologiques. Le second chapitre est consacré à l'étude d'un module 60 GHz intégré sur silicium haute-résistivité en technologie interposer silicium. Nous nous intéressons aux méthodes de caractérisation adaptées aux diverses briques technologiques du back-end silicium spécifique aux applications RF-millimétriques et notamment les interconnexions, les matériaux diélectriques ainsi que les antennes intégrées. La caractérisation inclut également un test d'émission-réception entre deux modules 60 GHz. Dans le troisième chapitre, nous proposons d'améliorer le module grâce à un nouveau design d'antennes utilisant le concept de Surface Haute-Impédance (SHI). Ce design est destiné à octroyer plus de compacité et plus de fiabilité au module tout en conservant ses performances électriques. Finalement, le quatrième chapitre détaille les étapes de fabrication du véhicule de test antennaire ainsi que des résultats de caractérisation des antennes et des nouveaux matériaux diélectriques utilisés pour l'empilement technologique

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

2023 Astrophotonics Roadmap: pathways to realizing multi-functional integrated astrophotonic instruments

This is the final version. Available on open access from IOP Publishing via the DOI in this recordData availability statement: The data that support the findings of this study are available upon reasonable request from the authors.Photonic technologies offer numerous functionalities that can be used to realize astrophotonic instruments. The most spectacular example to date is the ESO Gravity instrument at the Very Large Telescope in Chile that combines the light-gathering power of four 8 m telescopes through a complex photonic interferometer. Fully integrated astrophotonic devices stand to offer critical advantages for instrument development, including extreme miniaturization when operating at the diffraction-limit, as well as integration, superior thermal and mechanical stabilization owing to the small footprint, and high replicability offering significant cost savings. Numerous astrophotonic technologies have been developed to address shortcomings of conventional instruments to date, including for example the development of photonic lanterns to convert from multimode inputs to single mode outputs, complex aperiodic fiber Bragg gratings to filter OH emission from the atmosphere, complex beam combiners to enable long baseline interferometry with for example, ESO Gravity, and laser frequency combs for high precision spectral calibration of spectrometers. Despite these successes, the facility implementation of photonic solutions in astronomical instrumentation is currently limited because of (1) low throughputs from coupling to fibers, coupling fibers to chips, propagation and bend losses, device losses, etc, (2) difficulties with scaling to large channel count devices needed for large bandwidths and high resolutions, and (3) efficient integration of photonics with detectors, to name a few. In this roadmap, we identify 24 key areas that need further development. We outline the challenges and advances needed across those areas covering design tools, simulation capabilities, fabrication processes, the need for entirely new components, integration and hybridization and the characterization of devices. To realize these advances the astrophotonics community will have to work cooperatively with industrial partners who have more advanced manufacturing capabilities. With the advances described herein, multi-functional integrated instruments will be realized leading to novel observing capabilities for both ground and space based platforms, enabling new scientific studies and discoveries.National Science Foundation (NSF)NAS