An efficient mechanism for debugging RTL description

[[abstract]]In this paper, an efficient algorithm to diagnose design errors in RTL description is proposed. The diagnosis algorithm exploits the hierarchy available in RTL designs to locate design errors. Using data-path to reduce the number of error candidates and ensure that true errors are included in. According to the estimated probability, the most suspected error candidates would be reported first in the display. The advantages of the proposed method are simple and available.[[conferencedate]]20030630~20030702[[conferencelocation]]Calgary, Alta., Canad

[[alternative]]A Data-Path Based Verification and Diagnosis Mechanism for RTL Description of VLSI Circuit

計畫編號：NSC93-2215-E032-002研究期間：200408~200507研究經費：392,000[[abstract]]隨著數位雜性和速度與日遽增，設計者必須在高層次來設計電路才能符合市 場的需求，因為邏輯合成可作暫存器轉移層次﹙Register Transfer Level, RTL﹚ 到實際線路的轉換，所以現今的趨勢大部份是在暫存器轉移層次做設計的工作。 在現今設計的流程中，設計錯誤的發生大多於硬體描述語言﹙Hardware Description Languages, HDLs﹚行為描述的階段，實際的設計以及設計規格之 間在功能上的不吻合經常會發生。然而，因為現今的數位設計的複雜度越來越高 的情況之下，以手工的方式從程式中找到錯誤的位置越來越困難。 在這次計畫中，我們提供了以資料路徑為基礎的自動錯誤診斷之有效方法， 來找尋錯誤可能發生的範圍，對於這範圍，我們首先去除掉一些不可能造成錯誤 的敘述以獲得一個敘述的集合稱之為錯誤空間﹙error space﹚。再者，我們試著 評估在錯誤空間裡的敘述為真正造成錯誤的可能性，根據這可能性，我們以一個 優先次序將這些敘述顯示出來，藉此，來縮短除錯的時間。[[sponsorship]]行政院國家科學委員

Plug & Test at System Level via Testable TLM Primitives

With the evolution of Electronic System Level (ESL) design methodologies, we are experiencing an extensive use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems where details of the communication among modules are separated from the those of the implementation of functional units. This paper represents a first step toward the automatic insertion of testing capabilities at the transaction level by definition of testable TLM primitives. The use of testable TLM primitives should help designers to easily get testable transaction level descriptions implementing what we call a "Plug & Test" design methodology. The proposed approach is intended to work both with hardware and software implementations. In particular, in this paper we will focus on the design of a testable FIFO communication channel to show how designers are given the freedom of trading-off complexity, testability levels, and cos

Design for testability method at register transfer level

The testing of sequential circuit is more complex compared to combinational circuit because it needs a sequence of vectors to detect a fault. Its test cost increases with the complexity of the sequential circuit-under-test (CUT). Thus, design for testability (DFT) concept has been introduced to reduce testing complexity, as well as to improve testing effectiveness and efficiency. Scan technique is one of the mostly used DFT method. However, it has cost overhead in terms of area due to the number of added multiplexers for each flip-flop, and test application time due to shifting of test patterns. This research is motivated to introduce non-scan DFT method at register transfer level (RTL) in order to reduce test cost. DFT at RTL level is done based on functional information of the CUT and the connectivity of CUT registers. The process of chaining a register to another register is more effective in terms of area overhead and test application time. The first contribution of this work is the introduction of a non-scan DFT method at the RTL level that considers the information of controllability and observability of CUT that can be extracted from RTL description. It has been proven through simulation that the proposed method has higher fault coverage of around 90%, shorter test application time, shorter test generation time and 10% reduction in area overhead compared to other methods in literature for most benchmark circuits. The second contribution of this work is the introduction of built-in self-test (BIST) method at the RTL level which uses multiple input signature registers (MISRs) as BIST components instead of concurrent built-in logic block observers (CBILBOs). The selection of MISR as test register is based on extended minimum feedback vertex set algorithm. This new BIST method results in lower area overhead by about 32.9% and achieves similar higher fault coverage compared to concurrent BIST method. The introduction of non-scan DFT at the RTL level is done before logic synthesis process. Thus, the testability violations can be fixed without repeating the logic synthesis process during DFT insertion at the RTL level