12,768 research outputs found
Online Scheduled Execution of Quantum Circuits Protected by Surface Codes
Quantum circuits are the preferred formalism for expressing quantum
information processing tasks. Quantum circuit design automation methods mostly
use a waterfall approach and consider that high level circuit descriptions are
hardware agnostic. This assumption has lead to a static circuit perspective:
the number of quantum bits and quantum gates is determined before circuit
execution and everything is considered reliable with zero probability of
failure. Many different schemes for achieving reliable fault-tolerant quantum
computation exist, with different schemes suitable for different architectures.
A number of large experimental groups are developing architectures well suited
to being protected by surface quantum error correcting codes. Such circuits
could include unreliable logical elements, such as state distillation, whose
failure can be determined only after their actual execution. Therefore,
practical logical circuits, as envisaged by many groups, are likely to have a
dynamic structure. This requires an online scheduling of their execution: one
knows for sure what needs to be executed only after previous elements have
finished executing. This work shows that scheduling shares similarities with
place and route methods. The work also introduces the first online schedulers
of quantum circuits protected by surface codes. The work also highlights
scheduling efficiency by comparing the new methods with state of the art static
scheduling of surface code protected fault-tolerant circuits.Comment: accepted in QI
The future of computing beyond Moore's Law.
Moore's Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore's Law for 50 years is failing and is anticipated to flatten by 2025. This article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
Design Automation and Design Space Exploration for Quantum Computers
A major hurdle to the deployment of quantum linear systems algorithms and
recent quantum simulation algorithms lies in the difficulty to find inexpensive
reversible circuits for arithmetic using existing hand coded methods. Motivated
by recent advances in reversible logic synthesis, we synthesize arithmetic
circuits using classical design automation flows and tools. The combination of
classical and reversible logic synthesis enables the automatic design of large
components in reversible logic starting from well-known hardware description
languages such as Verilog. As a prototype example for our approach we
automatically generate high quality networks for the reciprocal , which is
necessary for quantum linear systems algorithms.Comment: 6 pages, 1 figure, in 2017 Design, Automation & Test in Europe
Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 201
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