2,358 research outputs found
A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 ÎŒm SOI CMOS
In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-ÎŒm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 ÎŒm wide, 10 mm long, 20 ÎŒm thick), achieving a crosstalk of â64.4 dB. The probe base (5 Ă 9 mm2) implements dual-band recording and a 1
Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors
The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 ”W. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 ”m TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit
Circuits for Analog Signal Processing Employing Unconventional Active Elements
DisertaÄnĂ prĂĄce se zabĂœvĂĄ zavĂĄdÄnĂm novĂœch struktur modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m a smĂĆĄenĂ©m reĆŸimu. FunkÄnost a chovĂĄnĂ tÄchto prvkĆŻ byly ovÄĆeny prostĆednictvĂm SPICE simulacĂ. V tĂ©to prĂĄci je zahrnuta Ćada simulacĂ, kterĂ© dokazujĂ pĆesnost a dobrĂ© vlastnosti tÄchto prvkĆŻ, pĆiÄemĆŸ velkĂœ dĆŻraz byl kladen na to, aby tyto prvky byly schopny pracovat pĆi nĂzkĂ©m napĂĄjecĂm napÄtĂ, jelikoĆŸ poptĂĄvka po pĆenosnĂœch elektronickĂœch zaĆĂzenĂch a implantabilnĂch zdravotnickĂœch pĆĂstrojĂch stĂĄle roste. Tyto pĆĂstroje jsou napĂĄjeny bateriemi a k tomu, aby byla prodlouĆŸena jejich ĆŸivotnost, trend navrhovĂĄnĂ analogovĂœch obvodĆŻ smÄĆuje k stĂĄle vÄtĆĄĂmu sniĆŸovĂĄnĂ spotĆeby a napĂĄjecĂho napÄtĂ. HlavnĂm pĆĂnosem tĂ©to prĂĄce je nĂĄvrh novĂœch CMOS struktur: CCII (Current Conveyor Second Generation) na zĂĄkladÄ BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na zĂĄkladÄ FG, transkonduktor na zĂĄkladÄ novĂ© techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na zĂĄkladÄ GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na zĂĄkladÄ GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na zĂĄkladÄ BD. DĂĄle je uvedeno nÄkolik zajĂmavĂœch aplikacĂ uĆŸĂvajĂcĂch vĂœĆĄe jmenovanĂ© prvky. ZĂskanĂ© vĂœsledky simulacĂ odpovĂdajĂ teoretickĂœm pĆedpokladĆŻm.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.
Electromagnetic Interference and Compatibility
Recent progress in the fields of Electrical and Electronic Engineering has created new application scenarios and new Electromagnetic Compatibility (EMC) challenges, along with novel tools and methodologies to address them. This volume, which collects the contributions published in the âElectromagnetic Interference and Compatibilityâ Special Issue of MDPI Electronics, provides a vivid picture of current research trends and new developments in the rapidly evolving, broad area of EMC, including contributions on EMC issues in digital communications, power electronics, and analog integrated circuits and sensors, along with signal and power integrity and electromagnetic interference (EMI) suppression properties of materials
Design of RC sinusoidal oscillator based on active building blocks
BakalĂĄrska prĂĄca je venovanĂĄ RC oscilĂĄtorom s pouĆŸitĂm funkÄnĂœch blokov a operaÄnĂœch zosilovaÄov. Na poÄiatku je urobenĂœ reĆĄerĆĄ literatĂșry zaoberajĂșcej sa konĆĄtrukciou a nĂĄvrhom RC oscilĂĄtorov, a pouĆŸitiu rĂŽznych funkÄnĂœch blokov pri tomto nĂĄvrhu. JednotlivĂ© funkÄnĂ© bloky sĂș diskutovanĂ© a sĂș vybranĂ© rĂŽzne zapojenia s pouĆŸitĂm tĂœchto blokov, ktorĂ© sĂș simulovanĂ© analĂœzou na poÄĂtaÄi pomocou PSpice a SNAP. Je overenĂœ vznik oscilĂĄciĂ a vplyv jednotlivĂœch sĂșÄiastok v zapojenĂ. V druhej Äasti sĂș realizovanĂ© vybranĂ© zapojenia a overenĂ© teoretickĂ© poznatky na praktickej realizĂĄcii. Ădaje zĂskanĂ© z poÄĂtaÄovej simulĂĄcie a praktickej realizĂĄcie sĂș potom porovnanĂ©, a taktieĆŸ jednotlivĂ© zapojenia sĂș porovnanĂ© medzi sebou.Thesis is focused on RC oscillators employing active building blocks and operational amplifiers. In the beginning, review of available literature talking about this topic is done. Different building blocks and circuits containing those blocks are picked and some of them simulated with PSpice and SNAP programs. Oscillation creation and influence of circuit components is verified. Those circuits are realized in practical application and simulation results are compared to those gained from real world circuits, also the chosen circuits are compared between each other.
Simple Setup for Measuring the Response to Differential Mode Noise of Common Mode Chokes
This work presents a technique to measure the attenuation of differential mode noise
provided by common mode chokes. The proposed setup is a simpler alternative to the balanced
setup commonly employed to that end, and its main advantage is that it avoids the use of auxiliary
circuits (baluns). We make use of a modal analysis of a high-frequency circuit model of the common
mode choke to identify the natural modes actually excited both in the standard balanced setup and
in the simpler alternative setup proposed here. This analysis demonstrates that both setups are
equivalent at low frequencies and makes it possible to identify the key differences between them
at high frequencies. To analyze the scope and interest of the proposed measurement technique we
have measured several commercial common mode chokes and we have thoroughly studied the
sensitivity of the measurements taken with the proposed setup to electric and magnetic couplings.
We have found that the proposed setup can be useful for quick assessment of the attenuation provided
by a common mode choke for differential mode noise in a frequency range that encompasses the
frequencies where most electromagnetic compatibility regulations impose limits to the conducted
emissions of electronic equipment.Ministerio de EconomĂa y Competitividad TEC2014-54097-RMinisterio de EconomĂa y Competitividad H2020-EU.3.4.5.6SCOPUS project ID 83194
Design of adaptive analog filters for magnetic front-end read channels
Esta tese estuda o projecto e o comportamento de filtros em tempo contĂnuo de
muito-alta-frequĂȘncia. A motivação deste trabalho foi a investigação de soluçÔes de filtragem
para canais de leitura em sistemas de gravação e reprodução de dados em suporte
magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a
1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste
trabalho, o råpido desenvolvimento das tecnologias de microelectrónica suscitou esforços
muito significativos a nĂvel mundial com o objectivo de se investigarem novas tĂ©cnicas
de realização de filtros em circuito integrado monolĂtico, especialmente em tecnologia
CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo
a diversos nĂveis hierĂĄrquicos do projecto, que conduziu Ă realização e caracterização
de soluçÔes com as caracterĂsticas desejadas.
Num primeiro nĂvel, este estudo aborda a questĂŁo conceptual da gravação e transmissĂŁo
de sinal bem como a escolha de bons modelos matemĂĄticos para o tratamento da
informação e a minimização de erro inerente Ă s aproximaçÔes na conformidade aos princĂpios
fĂsicos dos dispositivos caracterizados.
O trabalho principal da tese Ă© focado nos nĂveis hierĂĄrquicos da arquitectura do
canal de leitura e da realização em circuito integrado do seu bloco principal â o bloco de
filtragem. Ao nĂvel da arquitectura do canal de leitura, apresenta-se um estudo alargado
sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte
magnĂ©tico. Este desĂgnio aparece no Ăąmbito da proposta de uma solução de baixo custo,
baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia
digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization)
com base na igualização de sinal utilizando filtros integrados analógicos em tempo
contĂnuo.
Ao nĂvel do projecto de realização do bloco de filtragem e das tĂ©cnicas de implementação
de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que
a técnica baseada em circuitos de transcondutùncia e condensadores, também conhecida como filtros gm-C (ou transcondutùncia-C), é a mais adequada para a realização de filtros
adaptativos em muito-alta-frequĂȘncia. Definiram-se neste nĂvel hierĂĄrquico mais baixo,
dois subnĂveis de aprofundamento do estudo no Ăąmbito desta tese, nomeadamente: a pesquisa
e anålise de estruturas ideais no projecto de filtros recorrendo a representaçÔes no
espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de
circuitos de transcondutùncia para a implementação de filtros integrados analógicos em
tempo contĂnuo.
Na sequĂȘncia deste estudo, apresentam-se e comparam-se duas estruturas de filtros
no espaço de estados, correspondentes a duas soluçÔes alternativas para a realização de
um igualador adaptativo realizado por um filtro contĂnuo passa-tudo de terceira ordem,
para utilização num canal de leitura de dados em suporte magnético.
Como parte constituinte destes filtros, apresenta-se uma técnica de realização de
circuitos de transcondutùncia, e de realização de condensadores lineares usando matrizes
de transĂstores MOSFET para processamento de sinal em muito-alta-frequĂȘncia realizada
em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se
métodos de adaptação automåtica capazes de compensar os erros face aos valores nominais
dos componentes, devidos Ă s tolerĂąncias inerentes ao processo de fabrico, para os
quais apresentamos os resultados de simulação e de medição experimental obtidos.
Na sequĂȘncia deste estudo, resultou igualmente a apresentação de um circuito passĂvel
de constituir uma solução para o controlo de posicionamento da cabeça de leitura
em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto
Ă© um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutĂąncia
e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo
de igualação do canal de leitura.
Este bloco de filtragem foi projectado e incluĂdo num circuito integrado (Jaguar) de
controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em
Colorado Springs, e incluĂdo num produto comercial em parceria com uma empresa escocesa
utilizado em discos rĂgidos amovĂveis.This thesis studies the design and behavior of continuous-time very-high-frequency
filters. The motivation of this work was the search for filtering solutions for the readchannel
in recording and reproduction of data on magnetic media systems, with costs and
consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than
the available circuits. Accordingly, as was done in this work, the rapid development of
microelectronics technology raised very significant efforts worldwide in order to investigate
new techniques for implementing such filters in monolithic integrated circuit, especially
in CMOS technology (Complementary Metal Oxide Semiconductor). We present
a comparative study on different hierarchical levels of the project, which led to the realization
and characterization of solutions with the desired characteristics.
In the first level, this study addresses the conceptual question of recording and
transmission of signal and the choice of good mathematical models for the processing of
information and minimization of error inherent in the approaches and in accordance with
the principles of the characterized physical devices.
The main work of this thesis is focused on the hierarchical levels of the architecture
of the read channel and the integrated circuit implementation of its main block - the filtering
block. At the architecture level of the read channel this work presents a comprehensive
study on existing methodologies of adaptation and signal recovery of data on
magnetic media. This project appears in the sequence of the proposed solution for a lowcost,
low consumption, low voltage, low complexity, using CMOS digital technology for
the performance of a DFE (Decision Feedback Equalization) based on the equalization of
the signal using integrated analog filters in continuous time.
At the project level of implementation of the filtering block and techniques for implementing
filters and its building components, it was concluded that the technique based
on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate
for the implementation of very-high-frequency adaptive filters. We defined in
this lower level, two sub-levels of depth study for this thesis, namely: research and analysis
of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation
of continuous time integrated analog filters.
Following this study, we present and compare two filtering structures operating in
the space of states, corresponding to two alternatives for achieving a realization of an
adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a
read-channel for magnetic media devices.
As a constituent part of these filters, we present a technique for the realization of
transconductance circuits and for the implementation of linear capacitors using arrays of
MOSFET transistors for signal processing in very-high-frequency integrated circuits using
sub-micrometric CMOS technology. We present methods capable of automatic adjustment
and compensation for deviation errors in respect to the nominal values of the
components inherent to the tolerances of the fabrication process, for which we present
the simulation and experimental measurement results obtained.
Also as a result of this study, is the presentation of a circuit that provides a solution
for the control of the head positioning on recording/playback systems of data on magnetic
media. The proposed block is an adaptive first-order filter, based on the same transconductance
circuits and equalization techniques proposed and used in the implementation
of the adaptive filter for the equalization of the read channel.
This filter was designed and included in an integrated circuit (Jaguar) used to control
the positioning of the read-head done for ATMEL company in Colorado Springs, and
part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company
High Fidelity Satellite Navigation Receiver Front-End for Advanced Signal Quality Monitoring and Authentication
Over the last several years, interest in utilizing foreign satellite timing and navigation (satnav) signals to augment GPS has grown. Doing so is not without risks; foreign satnav signals must be vetted and determined to be trustworthy before use in military applications. Advanced signal quality monitoring methods can help to ensure that only authentic and reliable satnav signals are utilized. To effectively monitor and authenticate signals, the front-end must impress as little distortions upon the received signal as possible. The purpose of this study is to design, fabricate, and test the performance of a high-fidelity satnav receiver front-end for advanced monitoring of foreign and domestic space vehicle signals
Available Techniques for Magnetic Hard Disk Drive Read Channel Equalization
This paper presents an extensive, non-exhaustive, study of available hard disk drive read channel equalization techniques used in the storage and readback of magnetically stored information. The physical elements and basic principles of the storage processes are introduced together with the basic theoretical definitions and models. Both read and write processes in magnetic storage are explained along with the definition of simple key concepts such as user bit density, intersymbol interference, linear and areal density, read head pulse response models, and coding algorithm
- âŠ