Design of testbed and emulation tools

The research summarized was concerned with the design of testbed and emulation tools suitable to assist in projecting, with reasonable accuracy, the expected performance of highly concurrent computing systems on large, complete applications. Such testbed and emulation tools are intended for the eventual use of those exploring new concurrent system architectures and organizations, either as users or as designers of such systems. While a range of alternatives was considered, a software based set of hierarchical tools was chosen to provide maximum flexibility, to ease in moving to new computers as technology improves and to take advantage of the inherent reliability and availability of commercially available computing systems

Modular platform for research in microgrids

The present Ph.D. thesis has been developed following an Industrial Ph.D. program and verses on developing a commercial piece of equipment for teknoCEA, a spin-off company from CITCEA-UPC. The thesis is centered on developing power electronics-based emulation systems for research in microgrids. Lately, the use of power electronics-based emulation systems is drawing substantial attention in the field of microgrids because their characteristics substantially facilitate research in laboratory facilities. First, the suitability of different topologies for implementing an emulation platform is analyzed. The focus is set on the topologies adjustability to implement various types of emulation systems. The analysis determines the most appropriate number of legs for the platform. A comparative analysis is done between two-level and multi-level topologies to determine their suitability based on different aspects. Moreover, the analysis confirms the usefulness of wide-bandgap semiconductors for this type of application. Next, a control structure is proposed together with its implementation in a low-cost microcontroller based on a modular software architecture. The control strategy based on fractional proportional resonant controllers for AC emulation systems provides a control system with high control bandwidth while keeping a low computational cost. The control strategy for DC emulation systems is provided to reach a fast transient response and immunity to external disturbances, which is key for good emulation of electric systems. The modular software architecture provides a software framework easily adjustable to the needs of multiple emulation systems. That allows the implementation of the multiple control strategies with minimum changes. Additionally provides a graphical representation of the software architecture from a static and dynamic point of view. Last, the reliability of the proposed platform is assessed based on the reliability curves provided in the literature. The reliability analysis is centered on the semiconductors and capacitors. It provides evidence that emulation systems typical currents and voltages clearly affect their reliability. For the capacitors reliability assessment, a thermal modeling methodology is proposed to overcome the limitations of standard approximations. The methodology is based on anisotropic modeling of the capacitor winding. Finally, the reliability analysis establishes the guidelines to assess the platform reliability if a given mission profile is provided.La present tesi doctoral s'ha dut a terme seguint un programa de doctorat industrial. La tesi exposa el desenvolupament d'un equip comercial per a teknoCEA, una spin-off del CITCEA-UPC. La tesi es centra en el desenvolupament d'emuladors basats en electrònica de potència per recerca en el camp de les microxarxes. Darrerament, l'ús d'emuladors s'ha estès ja que les seves característiques faciliten molt la recerca en laboratoris. En primer lloc, s'analitza la idoneïtat de diferents topologies per implementar una plataforma d'emulació. El focus recau en la capacitat de diferents topologies per ajustar-se a la implementació de múltiples sistemes d'emulació. L'anàlisi determina el número òptim de branques. Un anàlisi comparatiu entre topologies dos nivells i multinivell permet determinar-ne la idoneïtat en funció de diferents aspectes. A continuació, es proposa una estructura de control juntament amb la seva implementació en un microcontrolador de baix cost a partir d'una arquitectura de programari modular. L'estratègia de control basada en controladors FPR (fractional proportional resonant) per a emuladors de corrent altern, proporciona un sistema de control amb un gran ample de banda amb un baix cost computacional. L'estratègia de control proposada per emuladors de corrent continu proporciona una resposta transitòria ràpida i elevada immunitat a pertorbacions, aspecte clau per a una bona emulació de sistemes elèctrics. L'arquitectura de programari modular proporciona un marc de programari fàcilment ajustable a les necessitats de múltiples emuladors. Això permet la implementació de les múltiples estratègies de control amb canvis mínims. A més, ofereix una representació gràfica de l'arquitectura del programari tant des d'un punt de vista estàtic com dinàmic. Finalment, s'avalua la fiabilitat de la plataforma a partir de les corbes de fiabilitat disponibles a la bibliografia científica. L'anàlisi es centra en els semiconductors i condensadors i proporciona evidència que els corrents i les tensions típics en emuladors afecten la seva fiabilitat. Per a l'avaluació de la fiabilitat dels condensadors, es proposa una metodologia de modelització tèrmica que permet superar les limitacions de les metodologies emprades típicament en la bibliografia científica. La metodologia es basa en el modelatge del bobinat del condensador com un element anisòtrop. Per últim, l'anàlisi de fiabilitat estableix les pautes per avaluar la fiabilitat de la plataforma en el cas que es proporcioni un perfil d'operació determinat.Postprint (published version

Intelligent redundant actuation system requirements and preliminary system design

Several redundant actuation system configurations were designed and demonstrated to satisfy the stringent operational requirements of advanced flight control systems. However, this has been accomplished largely through brute force hardware redundancy, resulting in significantly increased computational requirements on the flight control computers which perform the failure analysis and reconfiguration management. Modern technology now provides powerful, low-cost microprocessors which are effective in performing failure isolation and configuration management at the local actuator level. One such concept, called an Intelligent Redundant Actuation System (IRAS), significantly reduces the flight control computer requirements and performs the local tasks more comprehensively than previously feasible. The requirements and preliminary design of an experimental laboratory system capable of demonstrating the concept and sufficiently flexible to explore a variety of configurations are discussed

Co-simulation techniques based on virtual platforms for SoC design and verification in power electronics applications

En las últimas décadas, la inversión en el ámbito energético ha aumentado considerablemente. Actualmente, existen numerosas empresas que están desarrollando equipos como convertidores de potencia o máquinas eléctricas con sistemas de control de última generación. La tendencia actual es usar System-on-chips y Field Programmable Gate Arrays para implementar todo el sistema de control. Estos dispositivos facilitan el uso de algoritmos de control más complejos y eficientes, mejorando la eficiencia de los equipos y habilitando la integración de los sistemas renovables en la red eléctrica. Sin embargo, la complejidad de los sistemas de control también ha aumentado considerablemente y con ello la dificultad de su verificación. Los sistemas Hardware-in-the-loop (HIL) se han presentado como una solución para la verificación no destructiva de los equipos energéticos, evitando accidentes y pruebas de alto coste en bancos de ensayo. Los sistemas HIL simulan en tiempo real el comportamiento de la planta de potencia y su interfaz para realizar las pruebas con la placa de control en un entorno seguro. Esta tesis se centra en mejorar el proceso de verificación de los sistemas de control en aplicaciones de electrónica potencia. La contribución general es proporcionar una alternativa a al uso de los HIL para la verificación del hardware/software de la tarjeta de control. La alternativa se basa en la técnica de Software-in-the-loop (SIL) y trata de superar o abordar las limitaciones encontradas hasta la fecha en el SIL. Para mejorar las cualidades de SIL se ha desarrollado una herramienta software denominada COSIL que permite co-simular la implementación e integración final del sistema de control, sea software (CPU), hardware (FPGA) o una mezcla de software y hardware, al mismo tiempo que su interacción con la planta de potencia. Dicha plataforma puede trabajar en múltiples niveles de abstracción e incluye soporte para realizar co-simulación mixtas en distintos lenguajes como C o VHDL. A lo largo de la tesis se hace hincapié en mejorar una de las limitaciones de SIL, su baja velocidad de simulación. Se proponen diferentes soluciones como el uso de emuladores software, distintos niveles de abstracción del software y hardware, o relojes locales en los módulos de la FPGA. En especial se aporta un mecanismo de sincronizaron externa para el emulador software QEMU habilitando su emulación multi-core. Esta aportación habilita el uso de QEMU en plataformas virtuales de co-simulacion como COSIL. Toda la plataforma COSIL, incluido el uso de QEMU, se ha analizado bajo diferentes tipos de aplicaciones y bajo un proyecto industrial real. Su uso ha sido crítico para desarrollar y verificar el software y hardware del sistema de control de un convertidor de 400 kVA

Description and Optimization of Abstract Machines in a Dialect of Prolog

In order to achieve competitive performance, abstract machines for Prolog and related languages end up being large and intricate, and incorporate sophisticated optimizations, both at the design and at the implementation levels. At the same time, efficiency considerations make it necessary to use low-level languages in their implementation. This makes them laborious to code, optimize, and, especially, maintain and extend. Writing the abstract machine (and ancillary code) in a higher-level language can help tame this inherent complexity. We show how the semantics of most basic components of an efficient virtual machine for Prolog can be described using (a variant of) Prolog. These descriptions are then compiled to C and assembled to build a complete bytecode emulator. Thanks to the high level of the language used and its closeness to Prolog, the abstract machine description can be manipulated using standard Prolog compilation and optimization techniques with relative ease. We also show how, by applying program transformations selectively, we obtain abstract machine implementations whose performance can match and even exceed that of state-of-the-art, highly-tuned, hand-crafted emulators.Comment: 56 pages, 46 figures, 5 tables, To appear in Theory and Practice of Logic Programming (TPLP

2-wire time independent asynchronous communications

Communications both to and between low end microprocessors represents a real cost in a number of industrial and consumer products. This thesis starts by examining the properties of protocols that help to minimize these expenses and comes to the conclusion that the derived set of properties define a new category of communications protocol : Time Independent Asynchronous ( TIA) communications. To show the utility of the TIA category we develop a novel TIA protocol that uses only 2-wires and general IO pins on each host. The protocol is analyzed using the Petri net based STG ( Signal Transition Graph) which is widely use to model asynchronous logic. It is shown that STGs do not accurately model the behavior of software driven systems and so a modified form called STG-FT ( STG For Threads) is developed to better model software systems. A simulator is created to take an STG-FT model and perform a full reachability tree analysis to prove correctness and analyze livelock and deadlock properties. The simulator can also examine the full reachability tree for every possible system state ( the cross product of all sub-system states), and analyze deadlock and livelock issues related to unexpected inputs and unusual situations. Reachability pruning algorithms are developed which decrease the search tree by a factor of approximately 250 million. The 2-wire protocol is implemented between a PC and an Atmel Tiny26 microprocessor, there is also a variant that works between microprocessors. Testing verifies the simulation results including an avoidable livelock condition with data throughput peaking at a useful 50 kilobits/second in both directions. The first practical application of 2-wire TIA is part of a novel debugger for the Atmel Tiny26 microprocessor. The approach can be extended to any microprocessor with general IO pins. TIA communications, developed in this thesis, is a serious contender whenever low end microprocessors must communicate with other processors. Consumer and industrial products may be able to achieve cost saving by using this new protocol

Role of simulation and emulation in the development of Shuttle-Centaur (STS-Centaur)

To support the task of integrating the Centaur liquid-fueled upper-stage space vehicle into the space shuttle program. A system to simulate and emulate the STS-Centaur avionic flight system and its supporting ground control and checkout equipment was selected and designated the systems integration facility (SIF). Located in San Diego, California, the SIF is composed of integrated simulators that form a composite control system complement to the STS-Centaur airborne and avionic support equipment. An off-line capability to verify the system design of the Centaur airborne support equipment (CASE) and the Centaur avionic flight system is provided as well as a realistic medium for the development and integration of ground checkout and airborne control software programs. Each simulator is composed of prototype hardware, where feasible, to maximize configuration likeness. Where emulated flight or ground hardware is used, it provides physical characteristics (loads, signals, etc.) equivalent to those of the flight hardware. The hardware and software implementation of the SIF are described