FIPBLOX: a graphical interactive design tool for FIPSOC

FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)Red de Universidades con Carreras en Informática (RedUNCI

FIPBLOX: a graphical interactive design tool for FIPSOC

FIPSOC is a field programmable mixed-signal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core which can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe, in real time, internal digital and analog signals. This device is specially suitable for development and fast prototyping of mixed signal integrated applications. As FIPSOC project is currently under development, it has no yet any powerful tool for synthesis and a structural VHDL (components) approach is to be used for designing. Therefore, the user starts from simple design structures and through a bottom-up style must build more complex components. In this paper we present FIPBLOX, a tool that allows the user automatically generate VHDL code for implementing and customizing high-level modules using the basic resources provided by the FIPSOC FPGA.Eje: Arquitectura, Redes y Sistemas Operativos (ARSO)Red de Universidades con Carreras en Informática (RedUNCI

Aplicação de dispositivos analógicos reconfiguráveis

Mestrado em Engenharia Electrotécnica e de ComputadoresEsta Tese tem como principal objectivo efectuar um estudo sobre o funcionamento e aplicabilidade das FPAAs, um circuito integrado reprogramável que permite emular sistemas analógicos. São estudadas diversas tecnologias e modelos disponíveis no mercado. Trata-se de uma tecnologia recente que está ainda numa fase de desenvolvimento com vista a atingir a sua maturidade e uma maior penetração no mercado. Assim como nas FPGAs, a tecnologia FPAA tem como objectivo aumentar a produtividade, reduzindo tempo e gastos no desenvolvimento, facilitando futuras alterações com o mínimo de impacto no sistema em execução. No entanto, em circuitos analógicos mais complexos ainda apresenta algumas limitações quando comparada com os sistemas de electrónica analógica clássicos, nomeadamente as frequências de funcionamento e limitações no número de componentes que pode emular num único integrado. Contudo, existem grandes vantagens quando utilizada em sistemas de condicionamento de sinal, filtragem e controlo. Em termos de ensaio e implementação, esta Tese foca a utilização desta tecnologia para o controlo industrial. São realizadas duas implementações: o controlo de temperatura de um forno e o controlo de velocidade de um motor DC. Quer numa aplicação quer noutra, a FPAA faz a leitura do valor de referência pretendido e o valor real medido e, conforme o erro resultante, actua sobre o actuador de modo a controlar o sistema. São utilizados três métodos de controlo, nomeadamente o controlo simples por comparação (ON/OFF), controlo por PWM e controlo PID. Para cada uma das implementações é analisado o comportamento do sistema. Os resultados das experiências efectuadas confirmam a eficácia e desempenho das FPAAs no condicionamento de sinal e no controlo de sistemas.The objective of this thesis is to study the operation and applicability of the FPAAs, a reprogrammable chip that can emulate analog circuit systems. Several technologies and types of FPAAs available in the market are studied. This is a recent technology which is still in a development phase in order to reach its maturity and greater market penetration. As in FPGAs, the FPAA technology is aimed to increase the productivity, reducing the development time and facilitating future changes with minor impact on the implemented system. However, these devices still present some limitations when compared with the realization of complex analog systems, including the frequency of operation and limitations on the number of components that can be emulated in a single device. However, the FPAAs have major advantages when used in signal conditioning systems, filtering and control. The FPAA applications in this thesis are focused in the test and implementation of this technology for industrial control. Two applications are developed: a temperature control of an oven system and a DC motor speed control system. In both applications, the FPAA reads the desired reference value and the actual value of the measured variable and, as function of the resulting error, acts on the actuator to control the system. Three methods of control are used, namely ON/OFF control, PWM control and PID control. For each application the behavior of the system is analyzed. The obtained results from the two experiments confirm the effectiveness and performance of the FPAAs in the signal conditioning and automatic control areas

High-Performance Fpaa Design For Hierarchical Implementation Of Analog And Mixed-Signal Systems

The design complexity of today's IC has increased dramatically due to the high integration allowed by advanced CMOS VLSI process. A key to manage the increased design complexity while meeting the shortening time-to-market is design automation. In digital world, the field-programmable gate arrays (FPGAs) have evolved to play a very important role by providing ASIC-compatible design methodologies that include design-for-testability, design optimization and rapid prototyping. On the analog side, the drive towards shorter design cycles has demanded the development of high performance analog circuits that are configurable and suitable for CAD methodologies. Field-programmable analog arrays (FPAAs) are intended to achieve the benefits for analog system design as FPGAs have in the digital field. Despite of the obvious advantages of hierarchical analog design, namely short time-to-market and low non-recurring engineering (NRE) costs, this approach has some apparent disadvantages. The redundant devices and routing resources for programmability requires extra chip area, while switch and interconnect parasitics cause considerable performance degradation. To deliver a high-performance FPAA, effective methodologies must be developed to minimize those adversary effects. In this dissertation, three important aspects in the FPAA design are studied to achieve that goal: the programming technology, the configurable analog block (CAB) design and the routing architecture design. Enabled by the Laser MakelinkTM technology, which provides nearly ideal programmable switches, channel segmentation algorithms are developed to improve channel routability and reduce interconnect parasitics. Segmented routing are studied and performance metrics accounting for interconnect parasitics are proposed for performance-driven analog routing. For large scale arrays, buffer insertions are considered to further reduce interconnection delay and cross-coupling noise. A high-performance, highly flexible CAB is developed to realized both continuous-mode and switched-capacitor circuits. In the end, the implementation of an 8-bit, 50MSPS pipelined A/D converter using the proposed FPAA is presented as an example of the hierarchical analog design approach, with its key performance specifications discussed

Palmo : a novel pulsed based signal processing technique for programmable mixed-signal VLSI

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable

Diseño e implementación de arquitecturas dinámicamente reconfigurables basadas en microprocesador

Tesis doctoral inédita leída en la Universidad Autónoma de Madrid. Escuela Técnica Superior de Informática, Departamento de Ingeniería Informática. Fecha de lectura: 1-06-200