Deep Space Network information system architecture study

The purpose of this article is to describe an architecture for the Deep Space Network (DSN) information system in the years 2000-2010 and to provide guidelines for its evolution during the 1990s. The study scope is defined to be from the front-end areas at the antennas to the end users (spacecraft teams, principal investigators, archival storage systems, and non-NASA partners). The architectural vision provides guidance for major DSN implementation efforts during the next decade. A strong motivation for the study is an expected dramatic improvement in information-systems technologies, such as the following: computer processing, automation technology (including knowledge-based systems), networking and data transport, software and hardware engineering, and human-interface technology. The proposed Ground Information System has the following major features: unified architecture from the front-end area to the end user; open-systems standards to achieve interoperability; DSN production of level 0 data; delivery of level 0 data from the Deep Space Communications Complex, if desired; dedicated telemetry processors for each receiver; security against unauthorized access and errors; and highly automated monitor and control

TDRSS S-shuttle unique receiver equipment

Beginning with STS-9, the Tracking and Date Relay Satellite system (TDRSS) will start providing S- and Ku-band communications and tracking support to the Space Shuttle and its payloads. The most significant element of this support takes place at the TDRSS White Sands Ground Terminal, which processes the Shuttle return link S- and Ku-band signals. While Ku-band hardware available to other TDRSS users is also applied to Ku-Shuttle, stringent S-Shuttle link margins have precluded the application of the standard TDRSS S-band processing equipment to S-Shuttle. It was therfore found necessary to develop a unique S-Shuttle Receiver that embodies state-of-the-art digital technology and processing techniques. This receiver, developed by Motorola, Inc., enhances link margins by 1.5 dB relative to the standard S-band equipment and its bit error rate performance is within a few tenths of a dB of theory. An overview description of the Space Shuttle Receiver Equipment (SSRE) is presented which includes the presentation of block diagrams and salient design features. Selected, measured performance results are also presented

On a Hybrid Preamble/Soft-Output Demapper Approach for Time Synchronization for IEEE 802.15.6 Narrowband WBAN

In this paper, we present a maximum likelihood (ML) based time synchronization algorithm for Wireless Body Area Networks (WBAN). The proposed technique takes advantage of soft information retrieved from the soft demapper for the time delay estimation. This algorithm has a low complexity and is adapted to the frame structure specified by the IEEE 802.15.6 standard for the narrowband systems. Simulation results have shown good performance which approach the theoretical mean square error limit bound represented by the Cramer Rao Bound (CRB)

DSN advanced receiver: Breadboard description and test results

A breadboard Advanced Receiver for use in the Deep Space Network was designed, built, and tested in the laboratory. Field testing was also performed during Voyager Uranus encounter at DSS-13. The development of the breadboard is intended to lead towards implementation of the new receiver throughout the network. The receiver is described on a functional level and then in terms of more specific hardware and software architecture. The results of performance tests in the laboratory and in the field are given. Finally, there is a discussion of suggested improvements for the next phase of development

Optical Time-Frequency Packing: Principles, Design, Implementation, and Experimental Demonstration

Time-frequency packing (TFP) transmission provides the highest achievable spectral efficiency with a constrained symbol alphabet and detector complexity. In this work, the application of the TFP technique to fiber-optic systems is investigated and experimentally demonstrated. The main theoretical aspects, design guidelines, and implementation issues are discussed, focusing on those aspects which are peculiar to TFP systems. In particular, adaptive compensation of propagation impairments, matched filtering, and maximum a posteriori probability detection are obtained by a combination of a butterfly equalizer and four 8-state parallel Bahl-Cocke-Jelinek-Raviv (BCJR) detectors. A novel algorithm that ensures adaptive equalization, channel estimation, and a proper distribution of tasks between the equalizer and BCJR detectors is proposed. A set of irregular low-density parity-check codes with different rates is designed to operate at low error rates and approach the spectral efficiency limit achievable by TFP at different signal-to-noise ratios. An experimental demonstration of the designed system is finally provided with five dual-polarization QPSK-modulated optical carriers, densely packed in a 100 GHz bandwidth, employing a recirculating loop to test the performance of the system at different transmission distances.Comment: This paper has been accepted for publication in the IEEE/OSA Journal of Lightwave Technolog

Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication