Hardware/software codesign methodology for fuzzy controller implementation

This paper describes a HW/SW codesign methodology for the implementation of fuzzy controllers on a platform composed by a general-purpose microcontroller and specific processing elements implemented on FPGAs or ASICs. The different phases of the methodology, as well as the CAD tools used in each design stage, are presented, with emphasis on the fuzzy system development environment Xfuzzy. Also included is a practical application of the described methodology for the development of a fuzzy controller for a dosage system

FPGA implementation of embedded fuzzy controllers for robotic applications

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/soffivare solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle

FPGA Implementation of Embedded Fuzzy Controllers for Robotic Applications

Fuzzy-logic-based inference techniques provide efficient solutions for control problems in classical and emerging applications. However, the lack of specific design tools and systematic approaches for hardware implementation of complex fuzzy controllers limits the applicability of these techniques in modern microelectronics products. This paper discusses a design strategy that eases the implementation of embedded fuzzy controllers as systems on programmable chips. The development of the controllers is carried out by means of a reconfigurable platform based on field-programmable gate arrays. This platform combines specific hardware to implement fuzzy inference modules with a general-purpose processor, thus allowing the realization of hybrid hardware/software solutions. As happens to the components of the processing system, the specific fuzzy elements are conceived as configurable intellectual property modules in order to accelerate the controller design cycle. The design methodology and tool chain presented in this paper have been applied to the realization of a control system for solving the navigation tasks of an autonomous vehicle. © 2007 IEEE.Ministerio de Educación y Ciencia TEC2005-04359/MIC y DPI2005-02293Junta de Andalucía TIC2006-635 y TEP2006-37

Towards hardware acceleration of neuroevolution for multimedia processing applications on mobile devices

This paper addresses the problem of accelerating large artificial neural networks (ANN), whose topology and weights can evolve via the use of a genetic algorithm. The proposed digital hardware architecture is capable of processing any evolved network topology, whilst at the same time providing a good trade off between throughput, area and power consumption. The latter is vital for a longer battery life on mobile devices. The architecture uses multiple parallel arithmetic units in each processing element (PE). Memory partitioning and data caching are used to minimise the effects of PE pipeline stalling. A first order minimax polynomial approximation scheme, tuned via a genetic algorithm, is used for the activation function generator. Efficient arithmetic circuitry, which leverages modified Booth recoding, column compressors and carry save adders, is adopted throughout the design

Controladores difusos adaptativos como módulos de propiedad intelectual para FPGAs

La continua demanda por parte del mercado microelectrónico de aplicaciones novedosas, con elevados niveles de complejidad y tiempos de desarrollo cortos ha motivado el impulso de las técnicas de diseño basadas en el concepto de “reusabilidad” y el desarrollo de elementos de sistemas como módulos de propiedad intelectual o módulos IP. En esta comunicación se describe la implementación de controladores difusos como módulos IP para FPGAs. Los controladores operan como periféricos conectables al bus OPB para los procesadores disponibles en las FPGAs de Xilinx. El empleo de las memorias internas de las FPGAs para almacenar las bases de conocimiento permite definir o ajustar la funcionalidad en tiempo de operación.Ministerio de Educaión y Ciencia TEC2005-04359/MI

Soft computing techniques for video de-interlacing

This paper presents the application of soft computing techniques to video processing. Specially, the research work has been focused on de-interlacing task. It is necessary whenever the transmission standard uses an interlaced format but the receiver requires a progressive scanning, as happens in consumer displays such as LCDs and plasma. A simple hierarchical solution that combines three simple fuzzy logicbased constituents (interpolators) is presented in this paper. Each interpolator specialized in one of three key image features for de-interlacing: motion, edges, and possible repetition of picture areas. The resulting algorithm offers better results than others with less or similar computational cost. A very interesting result is that our algorithm is competitive with motion-compensated algorithm