Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

LFI 30 and 44 GHz receivers Back-End Modules

The 30 and 44 GHz Back End Modules (BEM) for the Planck Low Frequency Instrument are broadband receivers (20% relative bandwidth) working at room temperature. The signals coming from the Front End Module are amplified, band pass filtered and finally converted to DC by a detector diode. Each receiver has two identical branches following the differential scheme of the Planck radiometers. The BEM design is based on MMIC Low Noise Amplifiers using GaAs P-HEMT devices, microstrip filters and Schottky diode detectors. Their manufacturing development has included elegant breadboard prototypes and finally qualification and flight model units. Electrical, mechanical and environmental tests were carried out for the characterization and verification of the manufactured BEMs. A description of the 30 and 44 GHz Back End Modules of Planck-LFI radiometers is given, with details of the tests done to determine their electrical and environmental performances. The electrical performances of the 30 and 44 GHz Back End Modules: frequency response, effective bandwidth, equivalent noise temperature, 1/f noise and linearity are presented

Design of CMOS integrated frequency synthesizers for ultra-wideband wireless communications systems

Ultra¬wide band (UWB) system is a breakthrough in wireless communication, as it provides data rate one order higher than existing ones. This dissertation focuses on the design of CMOS integrated frequency synthesizer and its building blocks used in UWB system. A mixer¬based frequency synthesizer architecture is proposed to satisfy the agile frequency hopping requirement, which is no more than 9.5 ns, three orders faster than conventional phase¬locked loop (PLL)¬based synthesizers. Harmonic cancela¬tion technique is extended and applied to suppress the undesired harmonic mixing components. Simulation shows that sidebands at 2.4 GHz and 5 GHz are below 36 dBc from carrier. The frequency synthesizer contains a novel quadrature VCO based on the capacitive source degeneration structure. The QVCO tackles the jeopardous ambiguity of the oscillation frequency in conventional QVCOs. Measurement shows that the 5¬GHz CSD¬QVCO in 0.18 µm CMOS technology draws 5.2 mA current from a 1.2 V power supply. Its phase noise is ¬120 dBc at 3 MHz offset. Compared with existing phase shift LC QVCOs, the proposed CSD¬QVCO presents better phase noise and power efficiency. Finally, a novel injection locking frequency divider (ILFD) is presented. Im¬plemented with three stages in 0.18 µm CMOS technology, the ILFD draws 3¬mA current from a 1.8¬V power supply. It achieves multiple large division ratios as 6, 12, and 18 with all locking ranges greater than 1.7 GHz and injection frequency up to 11 GHz. Compared with other published ILFDs, the proposed ILFD achieves the largest division ratio with satisfactory locking range

Novel RF/Microwave Circuits And Systems for Lab on-Chip/on-Board Chemical Sensors

Recent research focuses on expanding the use of RF/Microwave circuits and systems to include multi-disciplinary applications. One example is the detection of the dielectric properties of chemicals and bio-chemicals at microwave frequencies, which is useful for pharmaceutical applications, food and drug safety, medical diagnosis and material characterization. Dielectric spectroscopy is also quite relevant to detect the frequency dispersive characteristics of materials over a wide frequency range for more accurate detection. In this dissertation, on-chip and on-board solutions for microwave chemical sensing are proposed. An example of an on-chip dielectric detection technique for chemical sensing is presented. An on-chip sensing capacitor, whose capacitance changes when exposed to material under test (MUT), is a part of an LC voltage-controlled oscillator (VCO). The VCO is embedded inside a frequency synthesizer to convert the change in the free runing frequency frequency of the VCO into a change of its input voltage. The system is implemented using 90 nm CMOS technology and the permittivities of MUTs are evaluated using a unique detection procedure in the 7-9 GHz frequency range with an accuracy of 3.7% in an area of 2.5 × 2.5 mm^2 with a power consumption of 16.5 mW. The system is also used for binary mixture detection with a fractional volume accuracy of 1-2%. An on-board miniaturized dielectric spectroscopy system for permittivity detec- tion is also presented. The sensor is based on the detection of the phase difference be- tween the input and output signals of cascaded broadband True-Time-Delay (TTD) cells. The sensing capacitor exposed to MUTs is a part of the TTD cell. The change of the permittivity results in a change of the phase of the microwave signal passing through the TTD cell. The system is fabricated on Rogers Duroid substrates with a total area of 8 × 7.2 cm2. The permittivities of MUTs are detected in the 1-8 GHz frequency range with a detection accuracy of 2%. Also, the sensor is used to extract the fractional volumes of mixtures with accuracy down to 1%. Additionally, multi-band and multi-standard communication systems motivate the trend to develop broadband front-ends covering all the standards for low cost and reduced chip area. Broadband amplifiers are key building blocks in wideband front-ends. A broadband resistive feedback low-noise amplifier (LNA) is presented using a composite cross-coupled CMOS pair for a higher gain and reduced noise figure. The LNA is implemented using 90 nm CMOS technology consuming 18 mW in an area of 0.06 mm2. The LNA shows a gain of 21 dB in the 2-2300 MHz frequency range, a minimum noise figure of 1.4 dB with an IIP3 of -1.5 dBm. Also, a four-stage distributed amplifier is presented providing bandwidth extension with 1-dB flat gain response up to 16 GHz. The flat extended bandwidth is provided using coupled inductors in the gate line with series peaking inductors in the cascode gain stages. The amplifier is fabricated using 180 nm CMOS technology in an area of 1.19 mm2 achieving a power gain of 10 dB, return losses better than 16 dB, noise figure of 3.6-4.9 dB and IIP3 of 0 dBm with 21 mW power consumption. All the implemented circuits and systems in this dissertation are validated, demonstrated and published in several IEEE Journals and Conferences

Millimeter-Wave CMOS Digitally Controlled Oscillators for Automotive Radars

All-Digital-Phase-Locked-Loops (ADPLLs) are ideal for integrated circuit implementations and effectively generate frequency chirps for Frequency-Modulated-Continuous-Wave (FMCW) radar. This dissertation discusses the design requirements for integrated ADPLL, which is used as chirp synthesizer for FMCW automotive radar and focuses on an analysis of the ADPLL performance based on the Digitally-Controlled-Oscillator (DCO) design parameters and the ADPLL configuration. The fundamental principles of the FMCW radar are reviewed and the importance of linear DCO for reliable operation of the synthesizer is discussed. A novel DCO, which achieves linear frequency tuning steps is designed by arranging the available minimum Metal-Oxide-Metal (MoM) capacitor in unique confconfigurations. The DCO prototype fabricated in 65 nm CMOS fullls the requirements of the 77 GHz automotive radar. The resultant linear DCO characterization can effectively drive a chirp generation system in complete FMCW automotive radar synthesizer

Frequency Multipliers in SiGe BiCMOS for Local Oscillator Generation in D-band Wireless Transceivers

Communications at millimeter-wave (mm-Wave) have drawn a lot of attention in recent years due to the wide available bandwidth which translates directly to higher data transmission capacity. Generation of the transceivers local oscillation (LO) is critical because many contrasting requirements, i.e. tuning range (TR), phase noise (PN), output power, and level of spurious tones, affect the system performance. Differently from what is commonly pursued at Radio Frequency, LO generation with a PLL embedding a VCO at the desired output frequency is not viable at mm-wave. A more promising approach consists of a PLL in the 10-20GHz range, where silicon VCOs feature the best figure of merit, followed by a frequency multiplier. In this thesis, a frequency multiplication chain is investigated to up-convert an LO signal from X-band to D-band by a multiplication factor of 12. The multiplication is done in steps of 3, 2, and 2. A sextupler chip comprises the tripler and the first doubler and the last doubler stage which upconverts the LO signal from E- to D-band is realized in a separate chip, all in a 55nm SiGe BiCMOS technology. The frequency tripler circuit is based on a novel circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a separate break-out chip and consuming 23mW of DC power, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% fractional bandwidth and robustness to power variation of the driving signal over a 15dB range. Including the E-band doubler, the sextupler chip achieves a peak output power of 1.7dBm at 74.4GHz and remains within 2dB variation from 70GHz to 82GHz, corresponding to 16% fractional BW. In this frequency range, the leakages of all harmonics are suppressed by more than 40dBc. The design of the D-band doubler was aimed at delivering high output power with high efficiency and high conversion gain. Toward this end, the efficiency of a push-push pair was improved by a stacked Colpitts oscillator to boost the power conversion gain by 10dB. Moreover, the common-collector configuration keeps separate the oscillator tank from the load, allowing independent optimization of the harmonic conversion efficiency and the load impedance for maximum power delivery. The measured performance of the test chip demonstrated Pout up to 8dBm at 130GHz with 13dB conversion gain and 6.3% Power Added Efficiency

Development of wideband radio channel measurement and modeling techniques for future radio systems

This thesis discusses the development of micro- and millimeterwave wideband radio channel measurement and modeling techniques for future radio networks. Characterization of the radio channel is needed for radio system, wireless network, and antenna design. A radio channel measurement system was designed for 2.154, 5.3 GHz and 60 GHz center frequencies, and completed at the two lower frequencies. The sounder uses a pseudonoise code in the transmitter. In the receiver, first a sliding correlator, and later direct digital sampling, where the impulse response is detected by digital post processing, were realized. Certain implementation questions, like link budget, effects of phase noise on impulse response and direction of arrival estimation, and achievable performance using the designed concept, are discussed. Measurement campaigns included in this thesis were realized at 5.3 GHz frequency in micro- and picocells. A comprehensive measurement campaign performed inside different buildings was thoroughly analyzed. Propagation mechanisms were studied and empirical models for both large scale fading and multipath propagation were developed. Propagation through walls, diffraction through doorways, and propagation paths outside the building were observed. Pathloss in LOS was lower than the free space pathloss, due to wave guiding effects. In NLOS situation difference in the pathloss models in different buildings was significant. Behavior of the spatial diversity was estimated on the basis of spatial correlation functions extracted from the measurement data; an antenna separation of a fraction of a wavelength gives sufficient de-correlation for significant diversity gain in indoor environments at 5.3 GHz in NLOS.reviewe

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Design and implementation of a frequency synthesizer for an IEEE 802.15.4/Zigbee transceiver

The frequency synthesizer, which performs the main role of carrier generation for the down-conversion/up-conversion operations, is a key building block in radio transceiver front-ends. The design of a synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee transceiver forms the core of this work. This thesis provides a step-by-step procedure for the design of a frequency synthesizer in a transceiver environment, from the mapping of standard-specifications to its integrated circuit implementation in a CMOS technology. The results show that careful system level planning leads to high-performance realizations of the synthesizer. A strategy of using different supply voltages to enhance the performance of each building block is discussed. A section is presented on layout and board level issues, especially for radio-frequency systems, and their effect on synthesizer performance. The synthesizer consumes 15.5 mW and meets the specifications of the 2.4 GHz IEEE 802.15.4/Zigbee standard. It is capable of 5 GHz operation with a VCO sensitivity of 135 MHz/V and a tuning range of 700 MHz. It can be seen that the adopted methodology can be used for the design of high-performance frequency synthesizers for any narrow-band wireless standard

Design and Analysis of a Wide Loop-Bandwidth RF Synthesizer Using Ring oscillator For DECT Receiver

Wireless communication devices including cordless phones and modern digital cellular systems (DCSs) use portable transceiver systems. The frequency synthesis of this type of transceiver system is done using a phase-locked loop oscillator. Traditional on-chip implementation of a complete phase-locked loop using a ring type voltage controlled oscillator contributes higher noise at the output. An alternative architecture, phase-locked loop (PLL) with wide loop-bandwidth, is proposed in this research to suppress the noise from the traditional ring oscillator. The proposed PLL is amendable to on-chip integration as well as commercially suitable for a Digital Enhancement Cordless Telephone (DECT) system which needs flexible noise margin. In this research, a 1.5552 GHz PLL-based frequency synthesizer is designed with a noisy ring oscillator. The wide loop-bandwidth approach is applied in designing the PLL to suppress the VCO noise. In this type of frequency synthesizer, the frequency divider is operated at higher frequencies with less noise and care is taken to design the delay flip-flops and logic gates that can be operated at higher frequencies. Current-mode control can be employed in designing the logic gates and the delay flip-flop to enhance the speed performance of the divider. An alternate approach in designing a high-speed divider using a current-mode control approach is also presented