VLSI Architecture and Design

Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible. The cost of communication will make designs enforcing locality superior to other types of designs. Scaling down feature sizes results in increase of the delay that wires introduce. The delay even of metal wires will become significant. Time tends to be a local property which will make the design of globally synchronous systems more difficult. Self-timed systems will eventually become a necessity. With the chip complexity measured in terms of logic devices increasing by more than an order of magnitude over the next few years the importance of efficient design methodologies and tools become crucial. Hierarchical and structured design are ways of dealing with the complexity of chip design. Structered design focuses on the information flow and enforces a high degree of regularity. Both hierarchical and structured design encourage the use of cell libraries. The geometry of the cells in such libraries should be parameterized so that for instance cells can adjust there size to neighboring cells and make the proper interconnection. Cells with this quality can be used as a basis for "Silicon Compilers"

A 16 [email protected] Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip

We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy inferences per second) with 8.6mW power consumption. It occupies 2.89mm 2 (including pads) in a CMOS 1μm single-poly technology. Measurements are given to demonstrate its performance. All the operations needed for fuzzy inference are realized on-chip using analog circuitry compatible with standard VLSI CMOS technologies. On-chip digital control and memory circuitry is also incorporated for programmability. The chip architecture and circuitry are based on our design methodology for neurofuzzy systems reported in [1]. A few architectural modifications are made to share circuitry among rules and, thus, obtain reduced area and power consumption. The chip parameters can be learned in situ, for operation in a changing environment, by using dedicated hardware-compatible learning algorithms [1][8

A simulation-based design method to transfer surface mount RF system to flip-chip die implementation

The flip-chip technology is a high chip density solution to meet the demand for very large scale integration design. For wireless sensor node or some similar RF applications, due to the growing requirements for the wearable and implantable implementations, flip-chip appears to be a leading technology to realize the integration and miniaturization. In this paper, flip-chip is considered as part of the whole system to affect the RF performance. A simulation based design is presented to transfer the surface mount PCB board to the flip-chip die package for the RF applications. Models are built by Q3D Extractor to extract the equivalent circuit based on the parasitic parameters of the interconnections, for both bare die and wire-bonding technologies. All the parameters and the PCB layout and stack-up are then modeled in the essential parts' design of the flip-chip RF circuit. By implementing simulation and optimization, a flip-chip package is re-designed by the parameters given by simulation sweep. Experimental results fit the simulation well for the comparison between pre-optimization and post-optimization of the bare die package's return loss performance. This design method could generally be used to transfer any surface mount PCB to flip-chip package for the RF systems or to predict the RF specifications of a RF system using the flip-chip technology

Simulation of droplet-based microfluidic lab-on-a-chip applications

This paper was presented at the 3rd Micro and Nano Flows Conference (MNF2011), which was held at the Makedonia Palace Hotel, Thessaloniki in Greece. The conference was organised by Brunel University and supported by the Italian Union of Thermofluiddynamics, Aristotle University of Thessaloniki, University of Thessaly, IPEM, the Process Intensification Network, the Institution of Mechanical Engineers, the Heat Transfer Society, HEXAG - the Heat Exchange Action Group, and the Energy Institute.Miniaturization of biological and chemical assays in lab-on-a-chip systems is a highly topical field of research. Droplet-based microfluidic chips are types of these miniaturized systems. They expand the capability of assays with special features that are unreached by traditional workflows. In particular, small sample volumes, independent separated reaction units, high throughput, automation and parallelization of assays are prominent features of droplet-based microfluidic devices. Full custom centric design of droplet-based microfluidic lab-on-a-chip technology implicates a high system integration level and design complexity. Therefore advanced development methodologies are needed, comparable with the methods in electronic design automation. Our design and simulation toolkit meets these requirements for an agile and low-risk development of custom lab-on-a-chip devices. The system simulation approach enables a fast and precise prediction of complex microfluidic networks. This fact is confirmed by reference and benchmark experiments. The results show that the simulation correctly reproduces the experimental measurements.The German BMBF and the EU in the projects DiNaMiD, signature 0315591B and NoE Photonics4Life, Grant Agreement number: 224014

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs

Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm2 and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3×3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.LOCUST IST2001—38 097VISTA TIC2003—09 817 - C02—01Office of Naval Research N000 140 210 88

MARTE based design flow for Partially Reconfigurable Systems-on-Chips

International audienceSystems-on-Chip (SoCs) are considered an integral solution for designing embedded systems, for targeting complex intensive parallel computation applications. As advances in SoC technology permit integration of increasing number of hardware resources on a single chip, the targeted application domains such as software-defined radio are become increasingly sophisticated. The fallout of this complexity is that the system design, particularly software design, does not evolve at the same pace as that of hardware leading to a significant productivity gap. Adaptivity and reconfigurability are also critical issues for SoCs which must be able to cope with end user environment and requirements

Organs-on-Chips in Drug Development: The Importance of Involving Stakeholders in Early Health Technology Assessment

Organs-on-chips are three-dimensional, microfluidic cell culture systems that simulate the function of tissues and organ subunits. Organ-on-chip systems are expected to contribute to drug candidate screening and the reduction of animal tests in preclinical drug development and may increase efficiency of these processes. To maximize the future impact of the technology on drug development, it is important to make informed decisions regarding the attributes and features of organs-on-chips even though the technology is still in a stage of early development. It is likely that different stakeholders in organ-on-chip development, such as engineers, biologists, regulatory scientists, and pharmaceutical researchers, will have different perspectives on how to maximize the future impact of the technology. Various aspects of organ-on-chip development, such as cost, materials, features, cell source, read-out technology, types of data, and compatibility with existing technology, will likely be judged differently by different stakeholders. Early health technology assessment (HTA) is needed in order to facilitate the essential integration of such potentially conflicting views in the process of technology development. In this critical review we discuss the potential impact of organs-on-chips on the drug development process, and we use a pilot study to give examples of how different stakeholders have different perspectives on attributes of organ-on-chip technology. As a future tool in early HTA of organs-on-chips, we suggest the use of multicriteria decision analysis (MCDA), which is a formal method to deal with multiple and conflicting criteria in technology development. We argue that it is essential to design and perform a comprehensive MCDA for organ-on-chip development, and so the future impact of this technology in the pharmaceutical industry can be maximized

Democratizing Digital Microfluidics by a Cloud-based Design and Manufacturing Platform

Akin to the impact that digital microelectronics had on electronic devices for information technology, digital microfluidics (DMF) was anticipated to transform fluidic devices for lab-on-a-chip (LoC) applications. However, despite a wealth of research and publications, electrowetting-on-dielectric (EWOD) DMF has not achieved the anticipated wide adoption, and commercialization has been painfully slow. By identifying the technological and resource hurdles in developing DMF chip and control systems as the culprit, we envision democratizing DMF by building a standardized design and manufacturing platform. To achieve this vision, we introduce a proof-of-concept cloud platform that empowers any user to design, obtain, and operate DMF chips (https://edroplets.org). For chip design, we establish a web-based EWOD chip design platform with layout rules and automated wire routing. For chip manufacturing, we build a web-based EWOD chip manufacturing platform and fabricate four types of EWOD chips (i.e., glass, paper, PCB, and TFT) to demonstrate the foundry service workflow. For chip control, we introduce a compact EWOD control system along with web-based operating software. Although industrial fabrication services are beyond the scope of this work, we hope this perspective will inspire academic and commercial stakeholders to join the initiative toward a DMF ecosystem for the masses

The Detection of Defects in a Niobium Tri-layer Process

Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 90000, the quality of the process has to be assured so as to realize these complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed test-structures for detection of the top-ranking defects, which will be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designed, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections