Orcc's Compa-Backend demonstration

International audienceThis paper presents the implementation of a video decoding application starting from its dataflow and CAL representations. Our objective is to demonstrate the ability of the Open RVC-CAL Compiler (Orcc) to generate code for embedded systems. For the demonstration, the video application will be an MPEG-4 Part2 decoder. The targeted architecture is a multi-core heterogeneous system deployed onto the Zynq platform from Xilinx

MOVES Highlights Research, Education During Annual Summit

For the tenth year running, NPS‘ Modeling, Virtual Environments and Simulation, or MOVES, Institute showed off their support of that effort during their annual Research and Education Summit from July 13-15, showcasing a variety of defense-based modeling and simulation research projects

Framing open innovation in start-ups' incubators: A complexity theory perspective

Recently, concepts and principles from the Complexity Theory (or, generally speaking, the complexity sciences) have been applied as a perspective for capturing the influence of the context, interaction, and adaption in the innovation processes, such as the ones enabled in the business incubators. The purpose of this paper is to implement a frame of reference for understanding the start-ups’ incubator as a complex system where innovation, learning, and self-organization take place. We build on the interfaces between the Complexity Theory (i.e., complexity sciences) and Open Innovation literature to identify principles, patterns, and conditions that frame the incubation practices as simple rules aimed to sustain the innovation process towards the creation of new ventures. Results from the multiple case studies conducted in five incubators show that the features of variety, nonlinear interaction, interdependence, autonomy, and emergence of the incubation process framed as a complex system are enabled in different ways by the combination of the open innovation practices and services provided by the start-ups’ incubators, including the provision of physical infrastructure, access to funding streams, experts/entrepreneurs networking, education/workshops, mentorship, and advice

Daily Eastern News: December 13, 1979

https://thekeep.eiu.edu/den_1979_dec/1008/thumbnail.jp

Daily Eastern News: December 13, 1979

https://thekeep.eiu.edu/den_1979_dec/1008/thumbnail.jp

Montana Kaimin, January 31, 1997

Student newspaper of the University of Montana, Missoula.https://scholarworks.umt.edu/studentnewspaper/10101/thumbnail.jp

Accurate Modeling of Fault Impact in Arithmetic Circuits

International audienceVarious methods have been proposed for fault detection and fault tolerance in digital integrated circuits. In the case of arithmetic circuits, the selection of an efficient method depends on several elements: type of operation, type(s) of operand(s), computation algorithms, internal representations of numbers, optimizations at architecture and circuit levels, and acceptable accuracy level (i.e. mathematical error) of the result(s) including both rounding errors and errors due to the faults.High-level mathematical models are not sufficient to capture the effect of faults in arithmetic circuits. Simulation of intensive fault scenarios in all components of the arithmetic circuit (data-path, control, gates with important fan-out such as some partial products generation in large multipliers, etc.) is widely used. But cycle accurate and bit accurate software simulations at gate level are too slow for large circuits and numerous fault scenarios. FPGA emulation is a popular method to speed-up fault simulation.In the demo, we will present an hardware-software platform dedicated to fault emulation for ASIC arithmetic circuits. The platform is based on a parallel cluster of Zynq FPGA cards and a Linux server. Various arithmetic circuits and fault models will be demonstrated in the context of digital signal and image processing

FOS: A Modular FPGA Operating System for Dynamic Workloads

With FPGAs now being deployed in the cloud and at the edge, there is a need for scalable design methods which can incorporate the heterogeneity present in the hardware and software components of FPGA systems. Moreover, these FPGA systems need to be maintainable and adaptable to changing workloads while improving accessibility for the application developers. However, current FPGA systems fail to achieve modularity and support for multi-tenancy due to dependencies between system components and lack of standardised abstraction layers. To solve this, we introduce a modular FPGA operating system -- FOS, which adopts a modular FPGA development flow to allow each system component to be changed and be agnostic to the heterogeneity of EDA tool versions, hardware and software layers. Further, to dynamically maximise the utilisation transparently from the users, FOS employs resource-elastic scheduling to arbitrate the FPGA resources in both time and spatial domain for any type of accelerators. Our evaluation on different FPGA boards shows that FOS can provide performance improvements in both single-tenant and multi-tenant environments while substantially reducing the development time and, at the same time, improving flexibility