969 research outputs found

    Product assurance technology for custom LSI/VLSI electronics

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    The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

    Expansion of CMOS array design techniques

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    The important features of the multiport (double entry) automatic placement and routing programs for standard cells are described. Measured performance and predicted performance were compared for seven CMOS/SOS array types and hybrids designed with the high speed CMOS/SOS cell family. The CMOS/SOS standard cell data sheets are listed and described

    Integrated Schottky logic

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    Preliminary candidate advanced avionics system for general aviation

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    An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered

    Satellite on-board processing for earth resources data

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    Results of a survey of earth resources user applications and their data requirements, earth resources multispectral scanner sensor technology, and preprocessing algorithms for correcting the sensor outputs and for data bulk reduction are presented along with a candidate data format. Computational requirements required to implement the data analysis algorithms are included along with a review of computer architectures and organizations. Computer architectures capable of handling the algorithm computational requirements are suggested and the environmental effects of an on-board processor discussed. By relating performance parameters to the system requirements of each of the user requirements the feasibility of on-board processing is determined for each user. A tradeoff analysis is performed to determine the sensitivity of results to each of the system parameters. Significant results and conclusions are discussed, and recommendations are presented

    VLSI technology and applications

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    Metal oxide semiconductor and GaAs devices are discussed. Digital and analog circuits are described. Applications to communications circuits are presented

    Scaling limit of digital circuits due to thermal noise

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    The error probability at a node of a digital circuit exposed to thermal noise agitation is investigated and the minimal dissipation–reliability relation for practical electronic circuits is derived. The digital circuit is modeled by an inverter chain with ideal transfer characteristics, and the error probability due to spurious data transfer caused by the thermal noise fluctuation is evaluated as a function of the node switching energy. The maximal error probability at each node allowed by the reliability requirement of the total system leads us to the minimal node energy dissipated per logical switching, which amounts to around 12 eV in the future 1010 gate system operated at a 10 GHz clock rate with a 104 FIT level reliability. In view of the device size-scaling trend of large-scale integrated circuits, the minimal node energy is expected to be reached at a feature size of 10–20 nm

    An LSI associative processor

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    This thesis is a design study of an associative processor. The processor is a two-dimensional word organized array of cells. Instructions and data are entered in an input register. Results ripple down the array to an output register. The design is distinguished by the absence of address decoding and response-resolution circuits. The associative processor array is meant to be driven by a small general-purpose computer
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