Design and Implementation of Low Power Time-To-Digital Converter using MGDI Technique

This paper introduces a novel Time to Digital Converter (TDC) architecture based on the Modified Gate Diffusion Input (MGDI) technique, which is derived from the well-established GDI method. Through the utilization of MGDI-based logic gates and digital circuitry, this innovative approach leads to a substantial reduction in the number of transistors required for implementation. As a result, it offers significant advantages in terms of circuit area, power consumption, and propagation delay, while simultaneously simplifying the complexity of the overall logic design. The functional blocks within the TDC have been optimized to efficiently process an internal clock frequency of 5MHz. This achievement is realized using cutting-edge 90nm MGDI technology, operating at a supply voltage of 1V. Practical implementation of this design can be carried out seamlessly with Cadence Virtuoso tools in the 90nm technology node. In essence, this research effort represents a promising advancement in the realm of time-to-digital conversion. By harnessing the capabilities of MGDI and its transistor-saving attributes, the proposed TDC not only enhances performance but also addresses critical concerns such as power efficiency and chip area utilization. These advancements make it a compelling choice for applications requiring precise time measurements, while the compatibility with contemporary technology nodes ensures its relevance and applicability in modern integrated circuit design

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

A 3-step Low-latency Low-Power Multichannel Time-to-Digital Converter based on Time Residual Amplifier

This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter is based on a three-step architecture. The first step uses a counter whereas the following ones are based on two kinds of Delay Line structures. A programmable time amplifier is used between the second and third steps to reach the final resolution of 24.4 ps in the standard mode of operation. The system makes use of common continuously stabilized master blocks that control trimmable slave blocks, in each channel, against the effects of global PVT variations. Thanks to this structure, the power consumption of a channel is considerably reduced when it does not process a hit, and limited to 2.2 mW when it processes a hit. In the 130 nm CMOS technology used for the prototype, the area of a TDC channel is only 0.051 mm2. This compactness combined with low power consumption is a key advantage for integration in multi-channel front-end chips. The performance of this new structure has been evaluated on prototype chips. Measurements show excellent timing performance over a wide range of operating temperatures (-40{\deg}C to 60{\deg}C) in agreement with our expectations. For example, the measured timing integral nonlinearity is better than 1 LSB (25 ps) and the overall timing precision is better than 21 ps RMS

High Performance Power Management Integrated Circuits for Portable Devices

abstract: Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application. In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency. The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Designs and calibration of delay-line based ADCs

Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. Time domain resolution can be increased by high speed delay cells. A GHz sampling rate can be easily achieved with low power. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. Thus, this dissertation addresses the linearity issue of delay line ADCs. First, a novel 11-bit hybrid ADC using flash and delay line architectures, where a 4-bit flash ADC is followed by a 7-bit delay-line ADC, is proposed. In this structure, the noise/error of the second stage delay-line ADC is attenuated at the hybrid ADC output, such that the overall performance would not be limited by the poor linearity of the delay-line ADC. The achieved figure of merit (FOM) of 33.8 fJ/conversion-step is competitive with state-of-the-art ADCs. Furthermore, the proposed ADC inherits accuracy and high speed from the flash ADC and the delay-line ADC, respectively. The inherited advantages strongly support the scalability of the proposed ADC to provide a better performance with low power in further scaled fabrication processes. Second, in order to remove the harmonic distortion of delay-line ADC, we present a technique which extends harmonic distortion correction (HDC) to digitally calibrate a delay-line ADC. In our simulation results, digital calibration improves SNDR from 25.6 dB to 42.5 dB by averaging $2^{27}$ sample points, which corresponds to a 0.86 second calibration time. Last, a multiple-pass delay line ADC is proposed to improve overall ADC performance in terms of speed and resolution. In this structure, a multiple-pass delay cell can be early triggered by the previous cell to increase speed. Also, phase interpolation is used to improve the effective number of bits. The design is designed and simulated in a commercial 40nm process technology. With 500MHz sampling rate, the multiple-pass delay line ADC achieves an SNDR of 37 dB and consumes 4.2 mW, which is competitive with other reported ADCs.Electrical and Computer Engineerin

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

A Physical Unclonable Function Based on Inter-Metal Layer Resistance Variations and an Evaluation of its Temperature and Voltage Stability

Keying material for encryption is stored as digital bistrings in non-volatile memory (NVM) on FPGAs and ASICs in current technologies. However, secrets stored this way are not secure against a determined adversary, who can use probing attacks to steal the secret. Physical Unclonable functions (PUFs) have emerged as an alternative. PUFs leverage random manufacturing variations as the source of entropy for generating random bitstrings, and incorporate an on-chip infrastructure for measuring and digitizing the corresponding variations in key electrical parameters, such as delay or voltage. PUFs are designed to reproduce a bitstring on demand and therefore eliminate the need for on-chip storage. In this dissertation, I propose a kind of PUF that measures resistance variations in inter-metal layers that define the power grid of the chip and evaluate its temperature and voltage stability. First, I introduce two implementations of a power grid-based PUF (PG-PUF). Then, I analyze the quality of bit strings generated without considering environmental variations from the PG-PUFs that leverage resistance variations in: 1) the power grid metal wires in 60 copies of a 90 nm chip and 2) in the power grid metal wires of 58 copies of a 65 nm chip. Next, I carry out a series of experiments in a set of 63 chips in IBM\u27s 90 nm technology at 9 TV corners, i.e., over all combination of 3 temperatures: -40oC, 25oC and 85oC and 3 voltages: nominal and +/-10% of the nominal supply voltage. The randomness, uniqueness and stability characteristics of bitstrings generated from PG-PUFs are evaluated. The stability of the PG-PUF and an on-chip voltage-to-digital (VDC) are also evaluated at 9 temperature-voltage corners. I introduce several techniques that have not been previously described, including a mechanism to eliminate voltage trends or \u27bias\u27 in the power grid voltage measurements, as well as a voltage threshold, Triple-Module-Redundancy (TMR) and majority voting scheme to identify and exclude unstable bits

Design, analysis and implementation of voltage sensor for power-constrained systems

PhD ThesisThanks to an extensive effort by the global research community, the electronic technology has significantly matured over the last decade. This technology has enabled certain operations which humans could not otherwise easily perform. For instance, electronic systems can be used to perform sensing, monitoring and even control operations in environments such as outer space, underground, under the sea or even inside the human body. The main difficulty for electronics operating in these environments is access to a reliable and permanent source of energy. Using batteries as the immediate solution for this problem has helped to provide energy for limited periods of time; however, regular maintenance and replacement are required. Consequently, battery solutions fail wherever replacing them is not possible or operation for long periods is needed. For such cases, researchers have proposed harvesting ambient energy and converting it into an electrical form. An important issue with energy harvesters is that their operation and output power depend critically on the amount of energy they receive and because ambient energy often tends to be sporadic in nature, energy harvesters cannot produce stable or fixed levels of power all of the time. Therefore, electronic devices powered in this way must be capable of adapting their operation to the energy status of the harvester. To achieve this, information on the energy available for use is needed. This can be provided by a sensor capable of measuring voltage. However, stable and fixed voltage and time references are a prerequisite of most traditional voltage measurement devices, but these generally do not exist in energy harvesting environments. A further challenge is that such a sensor also needs to be powered by the energy harvester’s unstable voltage. In this thesis, the design of a reference-free voltage sensor, which can operate with a varying voltage source, is provided based on the capture of a portion of the total energy which is directly related to II the energy being sensed. This energy is then used to power a computation which quantifies captured energy over time, with the information directly generated as digital code. The sensor was fabricated in the 180 nm technology node and successfully tested by performing voltage measurements over the range 1.8 V to 0.8 V

Modelling of Stratified Dielectric Medium Stripline Delay Devices

Problem of investigation of stripline delay devices in stratified dielectric medium is considered in the dissertation. In the first chapter scientific publications regarding modelling of stripline delay devices and microwave devices in planar stratified dielectric medium, issued from 1976 to 2014 year are analytically reviewed. Areas of applications, methods of analysis and design and problems in modelling and design are analyzed. In the second chapter models of coupled and multiconductor microstrip lines in nonhomogenous dielectric medium are analyzed. Conditions for ensuring normal wave propagation in the lines are researched. Such lines can serve as the basis for stripline meander delay line modelling. The possibilities of equalizing phase velocities for odd and even normal wave propagation in coupled striplines in stratified dielectric medium are analyzed. The effect of air microlayer in double shielded stripline devices is reseached by using the created model. Techniques for synthesis, i.e. obtaining constructional parameters according to the desired electrical characteristics of multiconductor microstrip lines operating in even and odd normal mode have been created and researched. The proposed technique is based on iterative calculation of characterisitics by changing parameters, until the desired characteristic value is obtained. Effect of equalizing phase velocities of electromagnetic wave in strips of microstrip meander delay line to frequency characteristics have been investigated. Meander delay line based on the multiconductor line operating in even mode was designed and its characteristics were calculated using commercial software. Influence of air microlayer in packaged double shielded meander stripline delay line has been investigated. The delay line was designed and its characteristics were calculated by two different techniques – the proposed modelling technique combined with S-matrix method and modelled with comercial software based on the method of moments. A prototype double shielded meander delay line has been produced and its characteristics have been measured in order to check the correctness of the model. Comparisson of calculations and measurement differed by no more than 2%