Optimizing CMOS circuits for low power using transistor reordering

This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power internal nodes of the gate. This power consumption depends on the switching activity and the equilibrium probabilities of the inputs of the gate. The model allows an exploration of the different configurations of a gate that are obtained by recording its transistors. Thus, the best configuration of each gate is selected and the overall power consumption of the circuit is reduced.Peer ReviewedPostprint (published version

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Subthreshold and gate leakage current analysis and reduction in VLSI circuits

CMOS technology has scaled aggressively over the past few decades in an effort to enhance functionality, speed and packing density per chip. As the feature sizes are scaling down to sub-100nm regime, leakage power is increasing significantly and is becoming the dominant component of the total power dissipation. Major contributors to the total leakage current in deep submicron regime are subthreshold and gate tunneling leakage currents. The leakage reduction techniques developed so far were mostly devoted to reducing subthreshold leakage. However, at sub-65nm feature sizes, gate leakage current grows faster and is expected to surpass subthreshold leakage current. In this work, an extensive analysis of the circuit level characteristics of subthreshold and gate leakage currents is performed at 45nm and 32nm feature sizes. The analysis provides several key observations on the interdependency of gate and subthreshold leakage currents. Based on these observations, a new leakage reduction technique is proposed that optimizes both the leakage currents. This technique identifies minimum leakage vectors for a given circuit based on the number of transistors in OFF state and their position in the stack. The effectiveness of the proposed technique is compared to most of the mainstream leakage reduction techniques by implementing them on ISCAS89 benchmark circuits. The proposed leakage reduction technique proved to be more effective in reducing gate leakage current than subthreshold leakage current. However, when combined with dual-threshold and variable-threshold CMOS techniques, substantial subthreshold leakage current reduction was also achieved. A total savings of 53% for subthreshold leakage current and 26% for gate leakage current are reported

Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits

In nanometer-scale CMOS technology, leakage power has become a major component of the total power dissipation due to the downscaling of threshold voltage and gate oxide thickness. The leakage power consumption has received even more attention by increasing demand for mobile devices. Since mobile devices spend a majority of their time in a standby mode, the leakage power savings in standby state is critical to extend battery lifetime. For this reason, low power has become a major factor in designing CMOS circuits. In this dissertation, we propose a novel transistor reordering methodology for leakage reduction. Unlike previous technique, the proposed method provides exact reordering rules for minimum leakage formation by considering all leakage components. Thus, this method formulates an optimized structure for leakage reduction even in complex CMOS logic gate, and can be used in combination with other leakage reduction techniques to achieve further improvement. We also propose a new standby leakage reduction methodology, leakage-aware body biasing, to overcome the shortcomings of a conventional Reverse Body Biasing (RBB) technique. The RBB technique has been used to reduce subthreshold leakage current. Therefore, this technique works well under subthreshold dominant region even though it has intrinsic structural drawbacks. However, such drawbacks cannot be overlooked anymore since gate leakage has become comparable to subthreshold leakage in nanometer-scale region. In addition, BTBT leakage also increases with technology scaling due to the higher doping concentration applied in each process technology. In these circumstances, the objective of leakage minimization is not a single leakage source but the overall leakage sources. The proposed leakage-aware body biasing technique, unlike conventional RBB technique, considers all major leakage sources to minimize the negative effects of existing body biasing approach. This can be achieved by intelligently applying body bias to appropriate CMOS network based on its status (on-/off-state) with the aid of a pin/transistor reordering technique

Energy Aware Design and Analysis for Synchronous and Asynchronous Circuits

Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however. have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available. Power awareness indicates the ability of the system power to scale with changing conditions and quality requirements. Scalability is an important figure-of-merit since it allows the end user to implement operational policy. just like the user of mobile multimedia equipment needs to select between better quality and longer battery operation time. This dissertation discusses power/energy optimization and performs analysis on both synchronous and asynchronous logic. The major contributions of this dissertation include: 1 ) A 2-Dimensional Pipeline Gating technique for synchronous pipelined circuits to improve their power awareness has been proposed. This technique gates the corresponding clock lines connected to registers in both vertical direction (the data flow direction) and horizontal direction (registers within each pipeline stage) based on current input precision. 2) Two energy reduction techniques, Signal Bypassing & Insertion and Zero Insertion. have been developed for NCL circuits. Both techniques use Nulls to replace redundant Data 0\u27s based on current input precision in order to reduce the switching activity while Signal Bypassing & Insertion is for non-pipelined NCI, circuits and Zero Insertion is for pipelined counterparts. A dynamic active-bit detection scheme is also developed as an expansion. 3) Two energy estimation techniques, Equivalent Inverter Modeling based on Input Mapping in transistor-level and Switching Activity Modeling in gate-level, have been proposed. The former one is for CMOS gates with feedbacks and the latter one is for NCL circuits

Optimization of power and delay in VLSI circuits using transistor sizing and input ordering

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 85-88).by Chin Hwee Tan.M.S

Circuit designs for low-power and SEU-hardened systems

The desire to have smaller and faster portable devices is one of the primary motivations for technology scaling. Though advancements in device physics are moving at a very good pace, they might not be aggressive enough for now-a-day technology scaling trends. As a result, the MOS devices used for present day integrated circuits are pushed to the limit in terms of performance, power consumption and robustness, which are the most critical criteria for almost all applications. Secondly, technology advancements have led to design of complex chips with increasing chip densities and higher operating speeds. The design of such high performance complex chips (microprocessors, digital signal processors, etc) has massively increased the power dissipation and, as a result, the operating temperatures of these integrated circuits. In addition, due to the aggressive technology scaling the heat withstanding capabilities of the circuits is reducing, thereby increasing the cost of packaging and heat sink units. This led to the increase in prominence for smarter and more robust low-power circuit and system designs. Apart from power consumption, another criterion affected by technology scaling is robustness of the design, particularly for critical applications (security, medical, finance, etc). Thus, the need for error free or error immune designs. Until recently, radiation effects were a major concern in space applications only. With technology scaling reaching nanometer level, terrestrial radiation has become a growing concern. As a result Single Event Upsets (SEUs) have become a major challenge to robust designs. Single event upset is a temporary change in the state of a device due to a particle strike (usually from the radiation belts or from cosmic rays) which may manifest as an error at the output. This thesis proposes a novel method for adaptive digital designs to efficiently work with the lowest possible power consumption. This new technique improves options in performance, robustness and power. The thesis also proposes a new dual data rate flipflop, which reduces the necessary clock speed by half, drastically reducing the power consumption. This new dual data rate flip-flop design culminates in a proposed unique radiation hardened dual data rate flip-flop, Firebird\u27. Firebird offers a valuable addition to the future circuit designs, especially with the increasing importance of the Single Event Upsets (SEUs) and power dissipation with technology scaling.\u2