Robust DC and efficient time-domain fast fault simulation

Purpose – Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (DC) solution is determined followed by a transient simulation. We improve the robustness and the e¿iciency of these simulations. Design/methodology/approach – Determining the DC solution can be very hard. For this we present an adaptive time domain source stepping procedure that can deal with controlled sources. The method can easily be combined with existing pseudo-transient procedures. The method is robust and e¿cient. In the subsequent transient simulation the solution of a fault is compared to a golden, fault-free, solution. A strategy is developed to e¿ciently simulate the faulty solutions until their moment of detection. Finding – We fully exploit the hierarchical structure the circuit in the simulation process to bypass parts of the circuit that appear to be una¿ected by the fault. Accurate prediction and e¿cient solution procedures lead to fast fault simulation. Originality/value – Our fast fault simulation helps to store a database with detectable deviations for each fault. If such a detectable output "matches" a result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault. One aims to detect as much as possible candidate faults. Because of the many options the simulations must be very e¿cient

Robust DC and efficient time-domain fast fault simulation

Purpose – Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, "golden", design of an electronic circuit. By fault simulation one simulates all situations. Normally this leads to a large list of simulations in which for each defect a steady-state (DC) solution is determined followed by a transient simulation. We improve the robustness and the e¿iciency of these simulations. Design/methodology/approach – Determining the DC solution can be very hard. For this we present an adaptive time domain source stepping procedure that can deal with controlled sources. The method can easily be combined with existing pseudo-transient procedures. The method is robust and e¿cient. In the subsequent transient simulation the solution of a fault is compared to a golden, fault-free, solution. A strategy is developed to e¿ciently simulate the faulty solutions until their moment of detection. Finding – We fully exploit the hierarchical structure the circuit in the simulation process to bypass parts of the circuit that appear to be una¿ected by the fault. Accurate prediction and e¿cient solution procedures lead to fast fault simulation. Originality/value – Our fast fault simulation helps to store a database with detectable deviations for each fault. If such a detectable output "matches" a result of a product that has been returned because of malfunctioning it helps to identify the subcircuit that may contain the real fault. One aims to detect as much as possible candidate faults. Because of the many options the simulations must be very e¿cient

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions

Моделювання відмов в інтегральних схемах

Магістерська робота «Моделювання відмов в інтегральних схемах» за об’ємом складає 76 сторінок, містить 22 таблиці, 43 ілюстрації, використано 14 інформаційних джерел. Актуальність роботи полягає у тому, що для аналогвих інтегральних схем відсутні чітко визначені методи верификації надійності через неперервний характер роботи аналогових схем, залежність параметрів від технологічних розкидів та умов навколишнього середовища. З введенням нових стандартів з безпеки інтегральних схем для автомобільної індустрії, критичним стала оцінка ризиків відмови чіпа в жорстких умовах навколишнього середовища і при старінні мікросхеми. Тому розробка універсального методу проведення тестів відмовостійкості розробленого пристрою є важливою задачею. Задачами дослідження є: визначення відмов, які можуть утворитися в схемі базуючись на механізмах відмов напівпровідникових елементів; побудова моделей, що достатньо повно описували б поведінку елементів схеми при відмовах; визначення закономірностей, за якими відмови можуть з’явитися у інтегральних схемах; розробка інструменту для автоматизованого внесення відмов у схему відповідно отриманих закономірностей. Об’єктом дослідження є аналогові інтегральні схеми до яких висуваються підвищені вимоги до безпеки та надійності. Предметом дослідження є оцінка рівня надійності таких схем. Методами дослідження є проведення симуляцій розроблених моделей та досліджуваної схеми у системах автоматизованого проектування. У данній роботі розглянуті основні механізми відмов, типові для сучасних напівпровідникових елементів. Розроблено моделі для симуляції поведінки окремих елементів з наявними дефектами. Запропоновано методи для внесення дефектів у схему, що мають найбільшу вірогідність утворення. Це дозволило зекономити час симуляції, не вносячи всі можливі відмови у схему. Розроблений метод був випробуваний на прикладі схеми, що проектується для використання в автомобільній промисловості, для оцінки її безпеки.Master’s thesis “Failures Simulation of Integrated Circuits” in volume is 76 pages, contains 22 tables, 43 figures. 14 sources were used. The relevance of the work lies in the fact that there are no strictly defined methods for reliability verification of analog integrated circuits due to the continuous nature of the analog circuit operation, dependence of the parameters on technological fluctuations and environmental conditions. With the introduction of new safety standards of integrated circuits for the automotive industry, the risk assessment of the chip failure in a harsh environment and due to aging became critical. Therefore, the development of an ultimate method for performing fault tolerance simulations of the device is an important task. The objectives of the study are: to define types of failures that can appear in the circuit, after investigating typical failure mechanisms of semiconductor devices; to develop the models that would precisely describe the behavior of the circuit elements with failure present; to determine the factors by which failures affect certain parts of IC; to develop a tool for automated fault injection according to the mentioned factors. The object of the research is analog integrated circuits with increased safety and reliability requirements. The subject of the study is the reliability estimation of such circuits. The research methods are simulations of the developed models and the circuit under study in CAD. In this paper, the basic mechanisms of failure, typical for modern semiconductor devices are considered. Models for simulating the behavior of circuit elements with failures have been developed. The methods for injecting faults with the highest probability of occurence were proposed. This allowed to save simulation time by not injecting all possible faults in the circuit. The developed method was tested on circuit that is designing for automotive application to assess its robustness

Optimization of the defect and fault simulation flow in analog and mixed signal circuits

Universidad de Sevilla. Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

Design and verification approaches for reliability and functional safety of analog integrated circuits

New breakthroughs in semiconductor design have enabled a rapid integration of semiconductor chips into systems that affect all aspects of the society. Examples of emerging systems include spacecraft, Internet of Things (IoT), intelligent automotive, and bio-implantable devices. Many of these systems are mission-critical or safety-critical, meaning that failure or malfunction may lead to severe economical losses, environmental damages or risks to human lives. In addition to performances improvement, the reliability and functional safety of the underlying integrated circuit (IC) have attracted more and more attention and have posed grand challenges for semiconductor industries. This dissertation introduces an approach for high performance voltage reference design and investigates two subjects that improve the reliability and functional safety of analog circuits. The first part of this dissertation studies design strategies of a low temperature-coefficient voltage reference generator, which is a fundamental building block and determines the maximum achievable performance of almost all analog/mixed-signal systems. The proposed method is targeted at extracting a physical quantity of the silicon bandgap, and has the potential of designing a voltage reference that has qualitatively better temperature dependence. An implementation of the proposed approach in GlobalFoundries 130nm process shows that the design can achieve temperature coefficients as low as 0.7ppm/°C over a temperature range of -40°C to 125°C over all process corners. The second part of this dissertation focuses on multi-states verification of analog circuits. The multiple DC equilibrium points or multi-states problem traces back to IC design. It is a well-known problem in many basic self-stabilized analog circuits because of the existence of positive feedback loops (PFLs). This work proposes systematic and automatic approaches for locating all PFLs to identify circuits vulnerable to undesired equilibrium states and methods for automatically identifying break-points to break all PFLs in the vulnerable circuits. The proposed methods make it possible to efficiently identify a circuit’s vulnerability to undesired operating points by considering circuit topology only, without the need for finding all possible solutions to a set of simultaneous nonlinear equations which is an open problem with no solution. Moreover, the automatic break-points identification enables easy use of homotopy analysis to guarantee absence of undesired states. The third part of this dissertation focuses on fault coverage simulation of analog circuits. This work describe two methods, one is to reduce the fault coverage estimation time and the other is to improve the fault coverage for analog circuits. The first method incorporates graph theory and sensitivity analysis and leads to dramatic reduction in fault coverage simulation time by 10’s of times for a moderately sized analog circuit. The second method discusses a systematic test-points selection technique to improve the analog fault coverage with simple DC tests and a concurrent sampling technique for monitoring these points. This work could be applied to manufacturing testing or for real-time fault detection

Defect Oriented Testing for Analog/Mixed-Signal Devices

Testing of Analog/Mixed-Signal (AMS) integrated circuits (ICs) has been one of the most challenging topics in the test technology community; this is because it is very time consuming and it is hard to distinguish between pass and fail as it is the case for digital circuits. For some applications, such as automotive industry, the quality requirements for AMS ICs can be as severe as zero Parts Per Million (PPM) level. This requires, in addition of optimizing test time, also test for all possible defects in the IC. Bridges and opens are the common defects considered for AMS circuits; they are analyzed in Defect Oriented Testing (DOT) flow in order to develop appropriate test program. With high/severe quality requirements new failure mechanisms have to be considered for test purposes. Investigating such defects and their impact on the quality is important especially for zero PPM level application. This thesis investigates the effect of dislocation defects for an NXP AMS IC which is an automotive product, manufactured in 140 nm technology. Dislocation defects cause leakage related failures while crossing a PN-junction of the device. It is very challenging in AMS testing to detect these defects. A schematic-based extraction methodology is proposed to extract the dislocation defects based on studying the cross-sections of different devices present in an IC. Using the proposed methodology for extraction, the defect list is limited to only 8% of the total active devices present in the IC. This is useful in guiding the failure analysis process and reducing the simulation effort considerably. These defects possess a high resistive signature and were simulated for different sets of resistance values. It was found that the detectability of these defects decreases as the resistance value is increased. Test selection algorithms such as ‘greedy’ and ‘unique detects first’ are used to obtain an optimal test set which is able to detect all the defects, including dislocation defects. The performance of both the algorithms in terms of test reduction is compared. The optimal test set obtained is used for validating the production data consisting of 1.3 million dies. The escaped ICs are diagnosed using a fault dictionary approach. The diagnosis results reveal that the current production data set does not suffer from dislocation defects. However, extra tests obtained for detecting dislocation defects can be kept for advanced technology nodes in the future, if these defects show up in the production environment.MicroelectronicsElectrical EngineeringElectrical Engineering, Mathematics and Computer Scienc