Deadlock-Free Routing in SpaceWire Onboard Network

In this article we consider the deadlock-free routing problem for onboard SpaceWire network with redundant devices. We work with static routing, it means that, routing tables are calculated and uploaded into the switches before launch the SpaceWire network. We solve deadlock-free problem with Up/Down routing approach, which is based on acyclic directed network graph. To build acyclic directed graph we modify the original algorithm of DFS based creating spanning tree. To find the routes of data transmission in the network we convert created directed graph to channel dependency graph. Also in this article we provide an example and explanation of our algorithms for deadlock-free routing in SpaceWire network

A method of computation for worst-case delay analysis on SpaceWire networks

SpaceWire is a standard for on-board satellite networks chosen by the ESA as the basis for future data-handling architectures. However, network designers need tools to ensure that the network is able to deliver critical messages on time. Current research only seek to determine probabilistic results for end-to-end delays on Wormhole networks like SpaceWire. This does not provide sufficient guarantee for critical traffic. Thus, in this paper, we propose a method to compute an upper-bound on the worst-case end-to-end delay of a packet in a SpaceWire network

Worst-case end-to-end delays evaluation for SpaceWire networks

SpaceWire is a standard for on-board satellite networks chosen by the ESA as the basis for multiplexing payload and control traffic on future data-handling architectures. However, network designers need tools to ensure that the network is able to deliver critical messages on time. Current research fails to address this needs for SpaceWire networks. On one hand, many papers only seek to determine probabilistic results for end-to-end delays on Wormhole networks like SpaceWire. This does not provide sufficient guarantee for critical traffic. On the other hand, a few papers give methods to determine maximum latencies on wormhole networks that, unlike SpaceWire, have dedicated real-time mechanisms built-in. Thus, in this paper, we propose an appropriate method to compute an upper-bound on the worst-case end-to-end delay of a packet in a SpaceWire network

Design and Simulation of Onboard SpaceWire Networks

The paper describes SpaceWire Automated Network Design and Simulation (SANDS) - the new CAD system for SpaceWire networks. SANDS system supports the full on-board network design and simulation flow, which begins from the network topology automated generation and finishes with getting the network structure, configuration and parameters setting, simulation results and statistics. The paper also provides use cases for SANDS application

Buffer-aware Worst Case Timing Analysis of Wormhole Network On Chip

A buffer-aware worst-case timing analysis of wormhole NoC is proposed in this paper to integrate the impact of buffer size on the different dependencies relationship between flows, i.e. direct and indirect blocking flows, and consequently the timing performance. First, more accurate definitions of direct and indirect blocking flows sets have been introduced to take into account the buffer size impact. Then, the modeling and worst-case timing analysis of wormhole NoC have been detailed, based on Network Calculus formalism and the newly defined blocking flows sets. This introduced approach has been illustrated in the case of a realistic NoC case study to show the trade off between latency and buffer size. The comparative analysis of our proposed Buffer-aware timing analysis with conventional approaches is conducted and noticeable enhancements in terms of maximum latency have been proved

Hardware demonstration of high-speed networks for satellite applications.

This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs

Distributed computing in space-based wireless sensor networks

This thesis investigates the application of distributed computing in general and wireless sensor networks in particular to space applications. Particularly, the thesis addresses issues related to the design of "space-based wireless sensor networks" that consist of ultra-small satellite nodes flying together in close formations. The design space of space-based wireless sensor networks is explored. Consequently, a methodology for designing space-based wireless sensor networks is proposed that is based on a modular architecture. The hardware modules take the form of 3-D Multi-Chip Modules (MCM). The design of hardware modules is demonstrated by designing a representative on-board computer module. The onboard computer module contains an FPGA which includes a system-on-chip architecture that is based on soft components and provides a degree of flexibility at the later stages of the design of the mission.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

7e Nederlandse testdag, Eindhoven, 8 November 2001 : proceedings

These are the proceedings of the seventh edition of the Nederlandse Testdag (a.k.a. Dutch Testing Day), held on November 8, 2001 in Eindhoven, The Netherlands. The increase in the complexity of software and hardware systems was the predominant concern in the software design of the last decades. This increase is still going on today. and mastering this complexity is possible, only by investigating, discussing and evaluating methods and techniques for testing such systems. The Nederlandse Testdag serves as a forum in which researchers from the industry and the academia discuss and present their latest experiences and theories in the area of testing. The initiative for organising the Nederlandse Testdag is, and has always been, the result of the combined efforts of the Dutch academia and the industry. The Nederlandse Testdag is an annual event which was first held in 1995. This year's edition again consists of one invited presentation by Jens Grabowski, on ITCN-3. and six regular presentations, both from the academia and from the industry. The presentations capture a broad field of the entire testing spectrum. In the presentation by Martin Gijsen (CMG), test automation for Graphical User Interface (GUI), dedicated and embedded systems according to the TestFrame methodology is explained. Klaas Mateboer (Collis) presents the test-tool Conclusion. René de Vries (University of Twente) reports on specification testing in practice and illustrates this by means of an example. In the presentation by Loe Feijs (Eindhoven University of Technology), testing is related to game-theory. Marcel Verhoef (Chess) and Bertil Oving (NLR) present their experiences using real-time simulation, UML and VDM to obtain more reliable spacecraft avionics. Finally, Ben van Buitenen (Baan), provides an insight in service pack testing: how to efficiently test customised software components and packages. The organisation of the Nederlandse Testdag is grateful for the sponsorship it received from the Eindhoven University of Technology, the Eindhoven Embedded Systems Institute, and the financial support from Dutch Research School IPA. We are very much indebted to CMG and Telelogic's willingness to sponsor this event financially. Over the years, both companies have profiled themselves as companies investing both time and resources in advancing the current state in testing. Finally, the organisation thanks Marcella de Rooij and EIize Russell for their organisational assistance

7e Nederlandse testdag, Eindhoven, 8 November 2001 : proceedings

These are the proceedings of the seventh edition of the Nederlandse Testdag (a.k.a. Dutch Testing Day), held on November 8, 2001 in Eindhoven, The Netherlands. The increase in the complexity of software and hardware systems was the predominant concern in the software design of the last decades. This increase is still going on today. and mastering this complexity is possible, only by investigating, discussing and evaluating methods and techniques for testing such systems. The Nederlandse Testdag serves as a forum in which researchers from the industry and the academia discuss and present their latest experiences and theories in the area of testing. The initiative for organising the Nederlandse Testdag is, and has always been, the result of the combined efforts of the Dutch academia and the industry. The Nederlandse Testdag is an annual event which was first held in 1995. This year's edition again consists of one invited presentation by Jens Grabowski, on ITCN-3. and six regular presentations, both from the academia and from the industry. The presentations capture a broad field of the entire testing spectrum. In the presentation by Martin Gijsen (CMG), test automation for Graphical User Interface (GUI), dedicated and embedded systems according to the TestFrame methodology is explained. Klaas Mateboer (Collis) presents the test-tool Conclusion. René de Vries (University of Twente) reports on specification testing in practice and illustrates this by means of an example. In the presentation by Loe Feijs (Eindhoven University of Technology), testing is related to game-theory. Marcel Verhoef (Chess) and Bertil Oving (NLR) present their experiences using real-time simulation, UML and VDM to obtain more reliable spacecraft avionics. Finally, Ben van Buitenen (Baan), provides an insight in service pack testing: how to efficiently test customised software components and packages. The organisation of the Nederlandse Testdag is grateful for the sponsorship it received from the Eindhoven University of Technology, the Eindhoven Embedded Systems Institute, and the financial support from Dutch Research School IPA. We are very much indebted to CMG and Telelogic's willingness to sponsor this event financially. Over the years, both companies have profiled themselves as companies investing both time and resources in advancing the current state in testing. Finally, the organisation thanks Marcella de Rooij and EIize Russell for their organisational assistance