Microarchitectural Techniques to Exploit Repetitive Computations and Values

La dependencia de datos es una de las principales razones que limitan el rendimiento de los procesadores actuales. Algunos estudios han demostrado, que las aplicaciones no pueden alcanzar más de una decena de instrucciones por ciclo en un procesador ideal, con la simple limitación de las dependencias de datos. Esto sugiere que, desarrollar técnicas que eviten la serialización causada por ellas, son importantes para acelerar el paralelismo a nivel de instrucción y será crucial en los microprocesadores del futuro.Además, la innovación y las mejoras tecnológicas en el diseño de los procesadores de los últimos diez años han sobrepasado los avances en el diseño del sistema de memoria. Por lo tanto, la cada vez mas grande diferencia de velocidades de procesador y memoria, ha motivado que, los actuales procesadores de alto rendimiento se centren en las organizaciones cache para tolerar las altas latencias de memoria. Las memorias cache solventan en parte esta diferencia de velocidades, pero a cambio introducen un aumento de área del procesador, un incremento del consumo energético y una mayor demanda de ancho de banda de memoria, de manera que pueden llegar a limitar el rendimiento del procesador.En esta tesis se proponen diversas técnicas microarquitectónicas que pueden aplicarse en diversas partes del procesador, tanto para mejorar el sistema de memoria, como para acelerar la ejecución de instrucciones. Algunas de ellas intentan suavizar la diferencia de velocidades entre el procesador y el sistema de memoria, mientras que otras intentan aliviar la serialización causada por las dependencias de datos. La idea fundamental, tras todas las técnicas propuestas, consiste en aprovechar el alto porcentaje de repetición de los programas convencionales.Las instrucciones ejecutadas por los programas de hoy en día, tienden a ser repetitivas, en el sentido que, muchos de los datos consumidos y producidos por ellas son frecuentemente los mismos. Esta tesis denomina la repetición de cualquier valor fuente y destino como Repetición de Valores, mientras que la repetición de valores fuente y operación de la instrucción se distingue como Repetición de Computaciones. De manera particular, las técnicas propuestas para mejorar el sistema de memoria se basan en explotar la repetición de valores producida por las instrucciones de almacenamiento, mientras que las técnicas propuestas para acelerar la ejecución de instrucciones, aprovechan la repetición de computaciones producida por todas las instrucciones.Data dependences are some of the most important hurdles that limit the performance of current microprocessors. Some studies have shown that some applications cannot achieve more than a few tens of instructions per cycle in an ideal processor with the sole limitation of data dependences. This suggests that techniques for avoiding the serialization caused by them are important for boosting the instruction-level parallelism and will be crucial for future microprocessors. Moreover, innovation and technological improvements in processor design have outpaced advances in memory design in the last ten years. Therefore, the increasing gap between processor and memory speeds has motivated that current high performance processors focus on cache memory organizations to tolerate growing memory latencies. Caches attempt to bridge this gap but do so at the expense of large amounts of die area, increment of the energy consumption and higher demand of memory bandwidth that can be progressively a greater limit to high performance.We propose several microarchitectural techniques that can be applied to various parts of current microprocessor designs to improve the memory system and to boost the execution of instructions. Some techniques attempt to ease the gap between processor and memory speeds, while the others attempt to alleviate the serialization caused by data dependences. The underlying aim behind all the proposed microarchitectural techniques is to exploit the repetitive behaviour in conventional programs. Instructions executed by real-world programs tend to be repetitious, in the sense that most of the data consumed and produced by several dynamic instructions are often the same. We refer to the repetition of any source or result value as Value Repetition and the repetition of source values and operation as Computation Repetition. In particular, the techniques proposed for improving the memory system are based on exploiting the value repetition produced by store instructions, while the techniques proposed for boosting the execution of instructions are based on exploiting the computation repetition produced by all the instructions

Banked microarchitectures for complexity-effective superscalar microprocessors

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 95-99).High performance superscalar microarchitectures exploit instruction-level parallelism (ILP) to improve processor performance by executing instructions out of program order and by speculating on branch instructions. Monolithic centralized structures with global communications, including issue windows and register files, are used to buffer in-flight instructions and to maintain machine state. These structures scale poorly to greater issue widths and deeper pipelines, as they must support simultaneous global accesses from all active instructions. The lack of scalability is exacerbated in future technologies, which have increasing global interconnect delay and a much greater emphasis on reducing both switching and leakage power. However, these fully orthogonal structures are over-engineered for typical use. Banked microarchitectures that consist of multiple interleaved banks of fewer ported cells can significantly reduce power, area, and latency of these structures.(cont.) Although banked structures exhibit a minor performance penalty, significant reductions in delay and power can potentially be used to increase clock rate and lead to more complexity-effective designs. There are two main contributions in this thesis. First, a speculative control scheme is proposed to simplify the complicated control logic that is involved in managing a less-ported banked register file for high-frequency superscalar processors. Second, the RingScalar architecture, a complexity-effective out-of-order superscalar microarchitecture, based on a ring topology of banked structures, is introduced and evaluated.by Jessica Hui-Chun Tseng.Ph.D

Using exercise to target maintenance factors of addictive behaviors

This research is prompted by the need to improve interventions for addictive behaviors. Research has identified several key biobehavioral mechanisms involved in the risk and maintenance of addiction, which are prime targets for novel interventions. The present dissertation aims to test whether we can effectively modify several factors predictive of relapse (e.g., low distress tolerance (DT), behavioral avoidance, and hypothalamic-pituitary-adrenal (HPA)-axis dysregulation) using physical activity interventions. The rationale for employing exercise for this application is supported by (1) decades of research attesting to the capacity for exercise to beneficially tap multiple biobehavioral systems, (2) more recent research supporting the clinical utility of exercise in substance use disorder treatment, and (3) emergent evidence supporting the potential of exercise as an appealing and accessible alternative or add-on to standard care. Study 1 extends the results of recent work by our group, which demonstrated efficacy for exercise to reduce anxiety sensitivity (AS), a form of distress intolerance reflecting vulnerability to somatic arousal. The results suggest that gender may be a moderator of this effect (Medina et al., 2014), with women responding less immediately than men. This observation underscores the need to further explore the treatment of distress-vulnerability in women, as well as potential merit in exploring alternatives to aerobic training. Accordingly, Studies 2 and 3 evaluated yoga for enhancing DT in females for whom distress vulnerability served to exacerbate maladaptive coping tendencies (e.g., smoking, overeating). Study 2 served as a proof of principle, wherein we examined the efficacy of Bikram yoga for enhancing DT in a sample of females with an elevated tendency to eat in response to stress or negative affect (i.e., conceptualized as an addictive behavior). Results were consistent with our hypothesis, showing that yoga enhanced self-reported emotional DT. Moreover, we found yoga primarily increased the absorption sub-facet of DT (defined as tendency for distress to absorb attentional resources), which, in turn, mediated reductions in self-reported emotional eating (Medina et al., 2015). In Study 3, we applied an 8-week hatha yoga (Vinyasa flow) intervention, aiming to address the contribution of elevated AS to early relapse in female smokers by targeting cortisol declines during the withdrawal phase of a quit attempt. Results did not support yoga as efficacious for altering cortisol, ameliorating subjective withdrawal, or achieving continuous abstinence post-quit. We speculate this was in part due to poor intervention adherence, highlighting the importance of including intervention components to address motivation for health behavior change. We discuss other limitations and future directions from our findings across studies.Psycholog

Low-cost and efficient fault detection and diagnosis schemes for modern cores

Continuous improvements in transistor scaling together with microarchitectural advances have made possible the widespread adoption of high-performance processors across all market segments. However, the growing reliability threats induced by technology scaling and by the complexity of designs are challenging the production of cheap yet robust systems. Soft error trends are haunting, especially for combinational logic, and parity and ECC codes are therefore becoming insufficient as combinational logic turns into the dominant source of soft errors. Furthermore, experts are warning about the need to also address intermittent and permanent faults during processor runtime, as increasing temperatures and device variations will accelerate inherent aging phenomena. These challenges specially threaten the commodity segments, which impose requirements that existing fault tolerance mechanisms cannot offer. Current techniques based on redundant execution were devised in a time when high penalties were assumed for the sake of high reliability levels. Novel light-weight techniques are therefore needed to enable fault protection in the mass market segments. The complexity of designs is making post-silicon validation extremely expensive. Validation costs exceed design costs, and the number of discovered bugs is growing, both during validation and once products hit the market. Fault localization and diagnosis are the biggest bottlenecks, magnified by huge detection latencies, limited internal observability, and costly server farms to generate test outputs. This thesis explores two directions to address some of the critical challenges introduced by unreliable technologies and by the limitations of current validation approaches. We first explore mechanisms for comprehensively detecting multiple sources of failures in modern processors during their lifetime (including transient, intermittent, permanent and also design bugs). Our solutions embrace a paradigm where fault tolerance is built based on exploiting high-level microarchitectural invariants that are reusable across designs, rather than relying on re-execution or ad-hoc block-level protection. To do so, we decompose the basic functionalities of processors into high-level tasks and propose three novel runtime verification solutions that combined enable global error detection: a computation/register dataflow checker, a memory dataflow checker, and a control flow checker. The techniques use the concept of end-to-end signatures and allow designers to adjust the fault coverage to their needs, by trading-off area, power and performance. Our fault injection studies reveal that our methods provide high coverage levels while causing significantly lower performance, power and area costs than existing techniques. Then, this thesis extends the applicability of the proposed error detection schemes to the validation phases. We present a fault localization and diagnosis solution for the memory dataflow by combining our error detection mechanism, a new low-cost logging mechanism and a diagnosis program. Selected internal activity is continuously traced and kept in a memory-resident log whose capacity can be expanded to suite validation needs. The solution can catch undiscovered bugs, reducing the dependence on simulation farms that compute golden outputs. Upon error detection, the diagnosis algorithm analyzes the log to automatically locate the bug, and also to determine its root cause. Our evaluations show that very high localization coverage and diagnosis accuracy can be obtained at very low performance and area costs. The net result is a simplification of current debugging practices, which are extremely manual, time consuming and cumbersome. Altogether, the integrated solutions proposed in this thesis capacitate the industry to deliver more reliable and correct processors as technology evolves into more complex designs and more vulnerable transistors.El continuo escalado de los transistores junto con los avances microarquitectónicos han posibilitado la presencia de potentes procesadores en todos los segmentos de mercado. Sin embargo, varios problemas de fiabilidad están desafiando la producción de sistemas robustos. Las predicciones de "soft errors" son inquietantes, especialmente para la lógica combinacional: soluciones como ECC o paridad se están volviendo insuficientes a medida que dicha lógica se convierte en la fuente predominante de soft errors. Además, los expertos están alertando acerca de la necesidad de detectar otras fuentes de fallos (causantes de errores permanentes e intermitentes) durante el tiempo de vida de los procesadores. Los segmentos "commodity" son los más vulnerables, ya que imponen unos requisitos que las técnicas actuales de fiabilidad no ofrecen. Estas soluciones (generalmente basadas en re-ejecución) fueron ideadas en un tiempo en el que con tal de alcanzar altos nivel de fiabilidad se asumían grandes costes. Son por tanto necesarias nuevas técnicas que permitan la protección contra fallos en los segmentos más populares. La complejidad de los diseños está encareciendo la validación "post-silicon". Su coste excede el de diseño, y el número de errores descubiertos está aumentando durante la validación y ya en manos de los clientes. La localización y el diagnóstico de errores son los mayores problemas, empeorados por las altas latencias en la manifestación de errores, por la poca observabilidad interna y por el coste de generar las señales esperadas. Esta tesis explora dos direcciones para tratar algunos de los retos causados por la creciente vulnerabilidad hardware y por las limitaciones de los enfoques de validación. Primero exploramos mecanismos para detectar múltiples fuentes de fallos durante el tiempo de vida de los procesadores (errores transitorios, intermitentes, permanentes y de diseño). Nuestras soluciones son de un paradigma donde la fiabilidad se construye explotando invariantes microarquitectónicos genéricos, en lugar de basarse en re-ejecución o en protección ad-hoc. Para ello descomponemos las funcionalidades básicas de un procesador y proponemos tres soluciones de `runtime verification' que combinadas permiten una detección de errores a nivel global. Estas tres soluciones son: un verificador de flujo de datos de registro y de computación, un verificador de flujo de datos de memoria y un verificador de flujo de control. Nuestras técnicas usan el concepto de firmas y permiten a los diseñadores ajustar los niveles de protección a sus necesidades, mediante compensaciones en área, consumo energético y rendimiento. Nuestros estudios de inyección de errores revelan que los métodos propuestos obtienen altos niveles de protección, a la vez que causan menos costes que las soluciones existentes. A continuación, esta tesis explora la aplicabilidad de estos esquemas a las fases de validación. Proponemos una solución de localización y diagnóstico de errores para el flujo de datos de memoria que combina nuestro mecanismo de detección de errores, junto con un mecanismo de logging de bajo coste y un programa de diagnóstico. Cierta actividad interna es continuamente registrada en una zona de memoria cuya capacidad puede ser expandida para satisfacer las necesidades de validación. La solución permite descubrir bugs, reduciendo la necesidad de calcular los resultados esperados. Al detectar un error, el algoritmo de diagnóstico analiza el registro para automáticamente localizar el bug y determinar su causa. Nuestros estudios muestran un alto grado de localización y de precisión de diagnóstico a un coste muy bajo de rendimiento y área. El resultado es una simplificación de las prácticas actuales de depuración, que son enormemente manuales, incómodas y largas. En conjunto, las soluciones de esta tesis capacitan a la industria a producir procesadores más fiables, a medida que la tecnología evoluciona hacia diseños más complejos y más vulnerables

Corporate Law and the Myth of Efficient Market Control

In recent times, there has been an unprecedented shift in power from managers to shareholders, a shift that realizes the long-held theoretical aspiration of market control of the corporation. This Article subjects the market control paradigm to comprehensive economic examination and finds it wanting. The market control paradigm relies on a narrow economic model that focuses on one problem only: management agency costs. With the rise of shareholder power, we need a wider lens that also takes in market prices, investor incentives, and information asymmetries. General equilibrium (GE) theory provides that lens. Several lessons follow from reference to this higher-order economic theory. First, the presumption that markets can efficiently coordinate the economy is unfounded, unless one relies on heroic assumptions. Second, GE shows that shareholders suffer from misaligned incentives, undercutting any normative program grounded in shareholder empowerment. The third lesson is negative, as there are no economically founded instructions for addressing the trade-offs between agency costs reduction and market inefficiency implied by the new shareholder corporation. Policy implications also follow. Given the lack of a clear normative template, only private ordering can be counted on to address each corporation\u27s specifc tradeoffs between agency costs and market inefficiency. This conclusion leads to an endorsement of Delaware\u27s equitable adjudication system, the flexibility of which is well suited to policing the bargaining process between managers and empowered shareholde

Corporate Law and the Myth of Efficient Market Control

In recent times, there has been an unprecedented shift in power from managers to shareholders, a shift that realizes the long-held theoretical aspiration of market control of the corporation. This Article subjects the market control paradigm to comprehensive economic examination and finds it wanting. The market control paradigm relies on a narrow economic model that focuses on one problem only, management agency costs. With the rise of shareholder power, we need a wider lens that also takes in market prices, investor incentives, and information asymmetries. General equilibrium theory (GE) provides that lens. Several lessons follow from reference to this higher-order economic theory. First, the presumption that markets can efficiently coordinate the economy is shown to be unfounded, unless one relies on heroic assumptions. Second, GE shows that shareholders suffer from misaligned incentives, undercutting any normative program grounded in shareholder empowerment. The third lesson is negative, as there are no economically-founded instructions for addressing the trade-offs between agency costs reduction and market inefficiency implied by the new shareholder corporation. Policy implications also follow. Given the lack of a clear normative template, only private ordering can be counted on to address each corporation’s specific tradeoffs between agency costs and market inefficiency. This conclusion leads to an endorsement of Delaware’s equitable adjudication system, the flexibility of which is well-suited to policing the bargaining process between managers and empowered shareholders

Low-Power and Error-Resilient VLSI Circuits and Systems.

Efficient low-power operation is critically important for the success of the next-generation signal processing applications. Device and supply voltage have been continuously scaled to meet a more constrained power envelope, but scaling has created resiliency challenges, including increasing timing faults and soft errors. Our research aims at designing low-power and robust circuits and systems for signal processing by drawing circuit, architecture, and algorithm approaches. To gain an insight into the system faults due to supply voltage reduction, we researched the two primary effects that determine the minimum supply voltage (VMIN) in Intel’s tri-gate CMOS technology, namely process variations and gate-dielectric soft breakdown. We determined that voltage scaling increases the timing window that sequential circuits are vulnerable. Thus, we proposed a new hold-time violation metric to define hold-time VMIN, which has been adopted as a new design standard. Device scaling increases soft errors which affect circuit reliability. Through extensive soft error characterization using two 65nm CMOS test chips, we studied the soft error mechanisms and its dependence on supply voltage and clock frequency. This study laid the foundation of the first 65nm DSP chip design for a NASA spaceflight project. To mitigate such random errors, we proposed a new confidence-driven architecture that effectively enhances the error resiliency of deeply scaled CMOS and post-CMOS circuits. Designing low-power resilient systems can effectively leverage application-specific algorithmic approaches. To explore design opportunities in the algorithmic domain, we demonstrate an application-specific detection and decoding processor for multiple-input multiple-output (MIMO) wireless communication. To enhance the receive error rate for a robust wireless communication, we designed a joint detection and decoding technique by enclosing detection and decoding in an iterative loop to enhance both interference cancellation and error reduction. A proof-of-concept chip design was fabricated for the next-generation 4x4 256QAM MIMO systems. Through algorithm-architecture optimizations and low-power circuit techniques, our design achieves significant improvements in throughput, energy efficiency and error rate, paving the way for future developments in this area.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110323/1/uchchen_1.pd

The accountancy profession and its professional and social responsibility: a systems theoretical approach to social and ethical accounting.

Doctoral Degree. University of KwaZulu-Natal, Pietermaritzburg.The accounting profession all over the world has found itself entangled in many scandals. Businesses, organizations and society at large rely on the financial information that is provided by the accounting profession. The financial information which accountants give remains critical to the overall economic wellbeing of society. In this regard, financial misinformation has led to serious economic crises in the world and sometimes to the collapse of powerful companies. Whilst the traditional understanding of the accounting profession was based on acquiring techniques and abiding by the codes of ethics that govern this profession, the experience of accountants is that their work place is characterized by chaos and complexity instead of orderliness which is implied in the codes and the popular technical practices of the profession that are mostly required in the office. Scholars have argued that the current type of education which is given to accounting students which is mainly based on technique acquisition does not prepare the student with professional competency when it comes to issues of ethical maturity which cannot be attained through the acquiring of professional qualification. The accountancy profession has a responsibility not only to shareholders or to the organizations which employed them but responsibility to stakeholders as well. The financial information which accountants provide is thus for the good of the whole of society and sometimes for the world as a whole. For this reason, some scholars have argued that accountants should be seen as guardians of the public interest. In the contemporary global neo-liberal capitalism, the question of whether accountants have any social responsibility when performing their professional responsibilities has been influenced by the debate on whether a business person has responsibilities towards society. The current global deregulation of financial markets has brought about the profession of accounting in a way that alienates the majority of the global citizens from benefiting from the financial information which is provided by this profession. The standardization of the global financial reporting is intended to facilitate the smooth flow of global capital in a way that serves the interests of investors, lenders and creditors who are in most cases the providers of capital on the global market. Accurate accounting and accountability are superficially undertaken with the aim of giving legitimacy to the shareholders of global capitalism. In light of the above observation, this study argues against the shareholder theory by insisting that shareholders are not the sole owners of business as there are others in society who are affected directly or indirectly by the activities of the business or organization. The implication of this argument is that the accounting profession must provide information that takes into consideration the expectations of all stakeholders. By adopting the stakeholder model of accounting,I have shown that monetary value requires reporting that takes into consideration social and environmental issues, which in most cases are not necessarily and solely determined by monetary value. The stakeholder perspective that has been adopted in this study finds its complementarity in general systems theory. Thus the accounting information as a sub-system should be seen as contributing to the suprasystem. Since systems theory is based on a holistic view of reality, it is argued that accounting education should be integrative whereby it incorporates information from other disciplines. From the perspective of general systems theory, any information that is provided should be seen as an abstraction from the suprasystem. Each system taken in isolation can only be seen as extending a partial view of reality. The study also argues that ethical and social accounting requires an inclusive approach in one’s professional outlook, especially when one takes into consideration the reality of complexity inherent in human society and social organization