Secure and Efficient RNS Approach for Elliptic Curve Cryptography

Scalar multiplication, the main operation in elliptic curve cryptographic protocols, is vulnerable to side-channel (SCA) and fault injection (FA) attacks. An efficient countermeasure for scalar multiplication can be provided by using alternative number systems like the Residue Number System (RNS). In RNS, a number is represented as a set of smaller numbers, where each one is the result of the modular reduction with a given moduli basis. Under certain requirements, a number can be uniquely transformed from the integers to the RNS domain (and vice versa) and all arithmetic operations can be performed in RNS. This representation provides an inherent SCA and FA resistance to many attacks and can be further enhanced by RNS arithmetic manipulation or more traditional algorithmic countermeasures. In this paper, extending our previous work, we explore the potentials of RNS as an SCA and FA countermeasure and provide an description of RNS based SCA and FA resistance means. We propose a secure and efficient Montgomery Power Ladder based scalar multiplication algorithm on RNS and discuss its SCAFA resistance. The proposed algorithm is implemented on an ARM Cortex A7 processor and its SCA-FA resistance is evaluated by collecting preliminary leakage trace results that validate our initial assumptions

Quantifying Muscle Fatigue of the Low Back during Repetitive Load Lifting Using Lyapunov Analysis

Background: Occupational low back disorders are often associated with exposure to work-related physical risk factors such as muscle fatigue in the low back.Objective: The objective of this study was to investigate the possible relationship between the divergence of the kinematic trajectories of the low back system and the different stages of fatigue during the execution of a repetitive lifting task.Methods: The patterns of the low back system were recorded using markers on specific vertebras during the repetitive load lifting from the floor to a 0.75 m height table. The maximum Lyapunov exponent, λmax of the recorded patterns was calculated from the x and y coordinates of the lower back markers using the algorithm proposed by Wolf.Results: The results of the λmax values determined three different sections of muscle fatigue which were also in agreement with the Borg’s clinical scale of perceived fatigue results. The assessment of the λmax values between the three different sections showed a descriptive point where the muscle fatigue accumulation may have resulted in a change of the low back control.Conclusion: Lyapunov exponent methodology could be a reliable methodology for ergonomists to provide an index to design the work/rest ratio ergonomically

Design and Implementation of Rijindael’s Encryption and Decryption Algorithm using NIOS-II Processor

One of the foremost vital problems in communication customary is that the secure transport protocols. This paper can offer a doable resolution for Rijindael’s encryption and decoding algorithmic program using NIOS II processor, provided by ALTERA to be enforced in FPGA. We are going to see the performance of Rijindael’s AES using NIOS II/e (economic), NIOS II/s (standard) and NIOS II/f (fast). The FPGA has the potential of data processing and hardware modification. The NIOS II is a versatile embedded processor family that represents high performance, lower overall cost, power consumption, complexity combining several functions into one chip. The look of the Rijindael algorithmic program supported “NIOS II + FPGA” are able to do a better processing speed whereas it occupies comparatively low resources. The AES algorithmic program is written in VHDL and is interfaced with the system using general purpose input and output (GPIO) and also the management part is enforced in software in NIOS II integrated development environment (IDE). The implementation is completed on Cyclone II FPGA kit. DOI: 10.17762/ijritcc2321-8169.160413

A priority-based budget scheduler with conservative dataflow model.

Currently, the guaranteed throughput of a stream processing application, mapped on a multi-processor system, can be computed with a conservative dataflow model, if only time division multiplex (TDM) schedulers are applied. A TDM scheduler is a budget scheduler. Budget schedulers can be characterized by two parameters: budget and replenishment interval. This paper introduces a priority-based budget scheduler (PBS), which is a budget scheduler that additionally associates a priority with every task. PBS improves the guaranteed minimum throughput of a stream processing application compared to TDM, given the same amount of resources. We construct a conservative dataflow model for a task scheduled by PBS. This dataflow model generalizes previous work, because it is valid for a sequence of execution times instead of one execution time per task which results in an improved accuracy of the model. Given this dataflow model, we can compute the guaranteed minimum throughput of the task graph that implements the stream processing application. Experiments confirm that a significantly higher guaranteed minimum throughput of the task graph can be obtained with PBS instead of TDM schedulers and that a conservative bound on the guaranteed throughput of the task graph can be computed with a dataflow model. Furthermore, our bound on the guaranteed throughput of the task graph is accurate, if the buffer capacities in the task graph do not affect the guaranteed throughput

Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study

Embedded real-time systems like those found in automotive, rail and aerospace, steadily require higher levels of guaranteed computing performance (and hence time predictability) motivated by the increasing number of functionalities provided by software. However, high-performance processor design is driven by the average-performance needs of mainstream market. To make things worse, changing those designs is hard since the embedded real-time market is comparatively a small market. A path to address this mismatch is designing low-complexity hardware features that favor time predictability and can be enabled/disabled not to affect average performance when performance guarantees are not required. In this line, we present the lessons learned designing and implementing LEOPARD, a four-core processor facilitating measurement-based timing analysis (widely used in most domains). LEOPARD has been designed adding low-overhead hardware mechanisms to a LEON3 processor baseline that allow capturing the impact of jittery resources (i.e. with variable latency) in the measurements performed at analysis time. In particular, at core level we handle the jitter of caches, TLBs and variable-latency floating point units; and at the chip level, we deal with contention so that time-composable timing guarantees can be obtained. The result of our applied study with a Space application shows how per-resource jitter is controlled facilitating the computation of high-quality WCET estimates

Optimal ILP-Based Approach for Gate Location Assignment and Scheduling in Quantum Circuits

Physical design and synthesis are two key processes of quantum circuit design methodology. The physical design process itself decomposes into scheduling, mapping, routing, and placement. In this paper, a mathematical model is proposed for mapping, routing, and scheduling in ion-trap technology in order to minimize latency of the circuit. The proposed model which is a mixed integer linear programming (MILP) model gives the optimal locations for gates and the best sequence of operations in terms of latency. Experimental results show that our scheme outperforms the other schemes for the attempted benchmarks

On Partition Metric Space, Index Function, and Data Compression

We discuss a metric structure on the set of partitions of a finite set induced by the Gini index and two applications of this metric: the identification of determining sets for index functions using techniques that originate in machine learning, and a data compression algorithm

The Extent and Coverage of Current Knowledge of Connected Health: Systematic Mapping Study

Background: This paper examines the development of the Connected Health research landscape with a view on providing a historical perspective on existing Connected Health research. Connected Health has become a rapidly growing research field as our healthcare system is facing pressured to become more proactive and patient centred. Objective: We aimed to identify the extent and coverage of the current body of knowledge in Connected Health. With this, we want to identify which topics have drawn the attention of Connected health researchers, and if there are gaps or interdisciplinary opportunities for further research. Methods: We used a systematic mapping study that combines scientific contributions from research on medicine, business, computer science and engineering. We analyse the papers with seven classification criteria, publication source, publication year, research types, empirical types, contribution types research topic and the condition studied in the paper. Results: Altogether, our search resulted in 208 papers which were analysed by a multidisciplinary group of researchers. Our results indicate a slow start for Connected Health research but a more recent steady upswing since 2013. The majority of papers proposed healthcare solutions (37%) or evaluated Connected Health approaches (23%). Case studies (28%) and experiments (26%) were the most popular forms of scientific validation employed. Diabetes, cancer, multiple sclerosis, and heart conditions are among the most prevalent conditions studied. Conclusions: We conclude that Connected Health research seems to be an established field of research, which has been growing strongly during the last five years. There seems to be more focus on technology driven research with a strong contribution from medicine, but business aspects of Connected health are not as much studied