1,106 research outputs found
DFT for controlled-impedance I/O buffers
This paper presents an architecture that enhances the testability of controlled-impedance buffers (CIBs). By testing CIBs digitally, the new architecture overcomes most of the problems with the traditional testing method. Most of these problems are test cost related. While reducing the test cost, the new architecture allows for higher test quality that even includes delay testing capabilities
Low power, compact charge coupled device signal processing system
A variety of charged coupled devices (CCDs) for performing programmable correlation for preprocessing environmental sensor data preparatory to its transmission to the ground were developed. A total of two separate ICs were developed and a third was evaluated. The first IC was a CCD chirp z transform IC capable of performing a 32 point DFT at frequencies to 1 MHz. All on chip circuitry operated as designed with the exception of the limited dynamic range caused by a fixed pattern noise due to interactions between the digital and analog circuits. The second IC developed was a 64 stage CCD analog/analog correlator for performing time domain correlation. Multiplier errors were found to be less than 1 percent at designed signal levels and less than 0.3 percent at the measured smaller levels. A prototype IC for performing time domain correlation was also evaluated
A built-in self-test technique for high speed analog-to-digital converters
Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009
Harmonic-by-harmonic time delay compensation Method for PHIL simulation of low impedance power systems
In PHIL simulations different time delays are introduced. Although it can be reduced, there is always some time delay. As a consequence, when the device under test is part of a low impedance power system such as: microgrids, marine or aero power systems, the simulation process becomes challenging due to the poor accuracy of the results achieved by the introduction of the time delay. Therefore, in order to accurately compensate for the inherent time delay introduced in Power Hardware in the Loop (PHIL) simulations, a method based on phase-shifting the reference voltage signal harmonic-by-harmonic and phase-by-phase is proposed. In this manner the time delay compensation will not affect to the system topology and therefore the dynamic behaviour of the original system will stay as it originally was in terms of power angles and V-I phase relationships for all the harmonics processed. In this paper, an experiment where the reference voltage is altered with 5th and 7th harmonics shows that the accuracy of PHIL simulations after the application of this compensation method is greatly improved compared with traditional methods. As a result, low impedance power systems are now able to experience an accurate PHIL simulation
Development of real-time cellular impedance analysis system
The cell impedance analysis technique is a label-free, non-invasive method, which simplifies sample preparation and allows applications requiring unmodified cell retrieval. However, traditional impedance measurement methods suffer from various problems (speed, bandwidth, accuracy) for extracting the cellular impedance information. This thesis proposes an improved system for extracting precise cellular impedance in real-time, with a wide bandwidth and satisfactory accuracy.
The system hardware consists of five main parts: a microelectrode array (MEA), a stimulation circuit, a sensing circuit, a multi-function card and a computer. The development of system hardware is explored. Accordingly, a novel bioimpedance measurement method coined digital auto balancing bridge method, which is improved from the traditional analogue auto balancing bridge circuitry, is realized for real-time cellular impedance measurement.
Two different digital bridge balancing algorithms are proposed and realized, which are based on least mean squares (LMS) algorithm and fast block LMS (FBLMS) algorithm for single- and multi-frequency measurements respectively. Details on their implementation in FPGA are discussed. The test results prove that the LMS-based algorithm is suitable for accelerating the measurement speed in single-frequency situation, whilst the FBLMS-based algorithm has advantages in stable convergence in multi-frequency applications.
A novel algorithm, called the All Phase Fast Fourier Transform (APFFT), is applied for post-processing of bioimpedance measurement results. Compared with the classical FFT algorithm, the APFFT significantly reduces spectral leakage caused by truncation error. Compared to the traditional FFT and Digital Quadrature Demodulation (DQD) methods, the APFFT shows excellent performance for extracting accurate phase and amplitude in the frequency spectrum.
Additionally, testing and evaluation of the realized system has been performed. The results show that our system achieved a satisfactory accuracy within a wide bandwidth, a fast measurement speed and a good repeatability. Furthermore, our system is compared with a commercial impedance analyzer (Agilent 4294A) in biological experiments. The results reveal that our system achieved a comparable accuracy to the commercial instrument in the biological experiments.
Finally, conclusions are given and the future work is proposed
The development of a power spectral density processor for C and L band airborne radar scatterometer sensor systems
A real-time signal processor was developed for the NASA/JSC L-and C-band airborne radar scatterometer sensor systems. The purpose of the effort was to reduce ground data processing costs. Conversion of two quadrature channels of data (like and cross polarized) was made to obtain Power Spectral Density (PSD) values. A chirp-z transform (CZT) approach was used to filter the Doppler return signal and improved high frequency and angular resolution was realized. The processors have been tested with record signals and excellent results were obtained. CZT filtering can be readily applied to scatterometers operating at other wavelengths by altering the sample frequency. The design of the hardware and software and the results of the performance tests are described in detail
System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits
This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand
(UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits.
The MultiBand OFDM (MB-OFDM) proposal for UWB communications has
received significant attention for the implementation of very high data rate (up to
480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion
quadrature mixer, and the overall radio system-level design are proposed for
an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented
in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with
interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in
quadrature with fast hopping, and a linear phase baseband section with 42dB of gain
programmability. The receiver IC mounted on a FR-4 substrate provides a maximum
gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a
2.5V supply.
Two BIT techniques for analog and RF circuits are developed. The goal is to reduce
the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the
magnitude and phase responses at different nodes of an analog circuit. A complete
prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is
demonstrated by performing frequency response measurements in a range of 1 to
130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF
RMS Detector and a methodology for its use in the built-in measurement of the gain and
1dB compression point of RF circuits are proposed to address the problem of on-chip
testing at RF frequencies. The proposed device generates a DC voltage proportional to
the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology
presents and input capacitance <15fF and occupies and area of 0.03mm2. The application
of these two techniques in combination with a loop-back test architecture significantly
enhances the testability of a wireless transceiver system
A challenge to the Delta G~0 interpretation of hydrogen evolution
Platinum is a nearly perfect catalyst for the hydrogen evolution reaction,
and its high activity has conventionally been explained by its
close-to-thermoneutral hydrogen binding energy (G~0). However, many candidate
non-precious metal catalysts bind hydrogen with similar strengths, but exhibit
orders-of-magnitude lower activity for this reaction. In this study, we employ
electronic structure methods that allow fully potential-dependent reaction
barriers to be calculated, in order to develop a complete working picture of
hydrogen evolution on platinum. Through the resulting ab initio microkinetic
models, we assess the mechanistic origins of Pt's high activity. Surprisingly,
we find that the G~0 hydrogen atoms are kinetically inert, and that the
kinetically active hydrogen atoms have G's much weaker, similar to that of
gold. These on-top hydrogens have particularly low barriers, which we compare
to those of gold, explaining the high reaction rates, and the exponential
variations in coverages can uniquely explain Pt's strong kinetic response to
the applied potential. This explains the unique reactivity of Pt that is missed
by conventional Sabatier analyses, and suggests true design criteria for
non-precious alternatives
Delta-Sigma Modulator based Compact Sensor Signal Acquisition Front-end System
The proposed delta-sigma modulator (M) based signal acquisition
architecture uses a differential difference amplifier (DDA) customized for dual
purpose roles, namely as instrumentation amplifier and as integrator of
M. The DDA also provides balanced high input impedance for signal
from sensors. Further, programmable input amplification is obtained by
adjustment of M feedback voltage. Implementation of other
functionalities, such as filtering and digitization have also been
incorporated. At circuit level, a difference of transconductance of DDA input
pairs has been proposed to reduce the effect of input resistor thermal noise of
front-end R-C integrator of the M. Besides, chopping has been
used for minimizing effect of Flicker noise. The resulting architecture is an
aggregation of functions of entire signal acquisition system within the single
block of M, and is useful for a multitude of dc-to-medium
frequency sensing and similar applications that require high precision at
reduced size and power. An implementation of this in 0.18-m CMOS process
has been presented, yielding a simulated peak signal-to-noise ratio of 80 dB
and dynamic range of 109dBFS in an input signal band of 1 kHz while consuming
100 W of power; with the measured signal-to-noise ratio being lower by
about 9 dB.Comment: 13 pages, 16 figure
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