Mapping DSP algorithms to a reconfigurable architecture Adaptive Wireless Networking (AWGN)

This report will discuss the Adaptive Wireless Networking project. The vision of the Adaptive Wireless Networking project will be given. The strategy of the project will be the implementation of multiple communication systems in dynamically reconfigurable heterogeneous hardware. An overview of a wireless LAN communication system, namely HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in a dynamically reconfigurable architecture are discussed. Suggestions for future activities in the Adaptive Wireless Networking project are also given

An alternative to IEEE 802.11ba: wake-up radio with legacy IEEE 802.11 transmitters

Current standardization process for Wake-up Radio (WuR) within the IEEE 802.11 Working Group, known as the IEEE 802.11ba, has brought interest to the IEEE 802.11-related technologies for the implementation of WuR systems. This paper proposes a new WuR system, where the Wake-up Transmitter (WuTx) is based on the legacy IEEE 802.11 Orthogonal Frequency Division Modulation (OFDM) Physical Layer (PHY) specification. Using the IEEE 802.11, OFDM PHY makes it possible for an IEEE 802.11a/g/n/ac transmitter to operate as WuTx for this WuR system. The WuTx generates a Wake-up Signal (WuS) coded with an amplitude-based digital modulation, achieving a bit rate of 250 kbps. This modulation, which we call Peak-Flat modulation, can be received using low-power receivers. A simulated proof of concept of the WuTx based on the IEEE 802.11g is presented and evaluated using MATLAB WLAN Toolbox. A method to generate the Peak-Flat modulated WuS from an IEEE 802.11a/g standard-compliant transmitter, using only software-level access, is explained. In addition, two possible low-power Wake-up Receiver (WuRx) architectures capable of decoding the presented modulation are proposed. The design of those receivers is generic enough to be used as a reference to compare the performance of the Peak-Flat Modulation with the other state-of-the-art approaches. The evaluation results conclude that the Peak-Flat modulation has similar performance compared to the other IEEE 802.11 WuR solutions on the reference receivers. Moreover, this solution provides a notorious advantage: legacy OFDM-based IEEE 802.11 transmitters can generate the Peak-Flat modulated WuS.Postprint (published version

Highly-configurable FPGA-based platform for wireless network research

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 155-164).Over the past few years, researchers have developed many cross-layer wireless protocols to improve the performance of wireless networks. Experimental evaluations of these protocols require both high-speed simulations and real-time on-air experimentations. Unfortunately, radios implemented in pure software are usually inadequate for either because they are typically two to three orders of magnitude slower than commodity hardware. FPGA-based platforms provide much better speeds but are quite difficult to modify because of the way high-speed designs are typically implemented by trading modularity for performance. Experimenting with cross-layer protocols requires a flexible way to convey information beyond the data itself from lower to higher layers, and a way for higher layers to configure lower layers dynamically and within some latency bounds. One also needs to be able to modify a layer's processing pipeline without triggering a cascade of changes. In this thesis, we discuss an alternative approach to implement a high-performance yet configurable radio design on an FPGA platform that satisfies these requirements. We propose that all modules in the design must possess two important design properties, namely latency-insensitivity and datadriven control, which facilitate modular refinements. We have developed Airblue, an FPGA-based radio, that has all these properties and runs at speeds comparable to commodity hardware. Our baseline design is 802.11g compliant and is able to achieve reliable communication for bit rates up to 24 Mbps. We show in the thesis that we can implement SoftRate, a cross-layer rate adaptation protocol, by modifying only 5.6% of the source code (967 lines). We also show that our modular design approach allows us to abstract the details of the FPGA platform from the main design, thus making the design portable across multiple FPGA platforms. By taking advantage of this virtualization capability, we were able to turn Airblue into a high-speed hardware software co-simulator with simulation speed beyond 20 Mbps.by Man Cheuk Ng.Ph.D

Space Station communications and tracking systems modeling and RF link simulation

In this final report, the effort spent on Space Station Communications and Tracking System Modeling and RF Link Simulation is described in detail. The effort is mainly divided into three parts: frequency division multiple access (FDMA) system simulation modeling and software implementation; a study on design and evaluation of a functional computerized RF link simulation/analysis system for Space Station; and a study on design and evaluation of simulation system architecture. This report documents the results of these studies. In addition, a separate User's Manual on Space Communications Simulation System (SCSS) (Version 1) documents the software developed for the Space Station FDMA communications system simulation. The final report, SCSS user's manual, and the software located in the NASA JSC system analysis division's VAX 750 computer together serve as the deliverables from LinCom for this project effort

Hardware Architectures of Visible Light Communication Transmitter and Receiver for Beacon-based Indoor Positioning Systems

High-speed applications of Visible Light Communications have been presented recently in which response times of photodiode-based VLC receivers are critical points. Typical VLC receiver routines, such as soft-decoding of run-length limited (RLL) codes and FEC codes was purely processed on embedded firmware, and potentially cause bottleneck at the receiver. To speed up the performance of receivers, ASIC-based VLC receiver could be the solution. Unfortunately, recent works on soft-decoding of RLL and FEC have shown that they are bulky and time-consuming computations. This causes hardware implementation of VLC receivers becomes heavy and unrealistic. In this paper, we introduce a compact Polar-code-based VLC receivers. in which flicker mitigation of the system can be guaranteed even without RLL codes. In particular, we utilized the centralized bit-probability distribution of a pre-scrambler and a Polar encoder to create a non-RLL flicker mitigation solution. At the receiver, a 3-bit soft-decision filter was implemented to analyze signals received from the VLC channel to extract log-likelihood ratio (LLR) values and feed them to the Polar decoder. Therefore, the proposed receiver could exploit the soft-decoding of the Polar decoder to improve the error-correction performance of the system. Due to the non-RLL characteristic, the receiver has a preeminent code-rate and a reduced complexity compared with RLL-based receivers. We present the proposed VLC receiver along with a novel very-large-scale integration (VLSI) architecture, and a synthesis of our design using FPGA/ASIC synthesis tools