Single event upset hardened CMOS combinational logic and clock buffer design

A radiation strike on semiconductor device may lead to charge collection, which may manifest as a wrong logic level causing failure. Soft errors or Single Event Upsets (SEU) caused by radiation strikes are one of the main failure modes in a VLSI circuit. Previous work predicts that soft error rate may dominate the failure rate in VLSI circuit compared to all other failure modes put together. The issue of single event upsets (SEU) need to be addressed such that the failure rate of the chips dues to SEU is in the acceptable range. Memory circuits are designed to be error free with the help of error correction codes. Technology scaling is driving up the SEU rate of combinational logic and it is predicted that the soft error rate (SER) of combinational logic may dominate the SER of unpro-tected memory by the year 2011. Hence a robust combinational logic methodology must be designed for SEU hardening. Recent studies have also shown that clock distribution network is becoming increasingly vulnerable to radiation strike due to reduced capaci-tance at the clock leaf node. A strike on clock leaf node may propagate to many flip-flops increasing the system SER considerably. In this thesis we propose a novel method to improve the SER of the circuit by filtering single event upsets in the combinational logic and clock distribution network. Our ap-proach results in minimal circuit overhead and also requires minimal effort by the de-signer to implement the proposed method. In this thesis we focus on preventing the propagation of SEU rather than eliminating the SEU on each sensitive gate

CDM Robust & Low Noise ESD protection circuits

In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, product reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are scaling down, while ESD energy remains the same, VLSIs are becoming more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. Hence, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Furthermore with scaling, the integration of analog blocks such as ADC, PLL’s, DLL’s, oscillator etc. on digital chips has provided cheap system on chip (SOC) solutions. However, when analog and digital chip are combined into single mixed-signal chip, on-chip noise coupling from the digital to the analog circuitry through ESD protection circuits becomes a big concern. Thus, increasing supply noise isolation while ensuring the ESD protection robustness is also a big challenge. In this thesis, several ESD protection circuits and devices have been proposed to address the critical issues like increased leakage current, slower turn-on time of devices, increased susceptibility to power supply isolation etc. The proposed ESD protection circuits/devices have been classified into two categories: Pad based ESD protection in which the ESD protection circuits are placed in the I/O pads, and Rail based ESD in which ESD protection circuit is placed between power supplies. In our research, both these aspects have been investigated. The Silicon Controlled Rectifier (SCR) based devices have been used for Pad ESD protection as they have highest ESD protection level per unit area. Two novel devices Darlington based SCR (DSCR) and NMOS Darlington based SCR (NMOS-DSCR) having faster turn-on time, lower first breakdown voltage and low capacitance have been proposed. The transient clamps have been investigated and optimized for Rail based ESD protection. In this research, we have addressed the issue of leakage current in transient clamps. A methodology has been purposed to reduce the leakage current by more than 200,000 times without having major impact on the ESD performance. Also, the issue of noise coupling from digital supply to analog supply through the ESD protection circuits has been addressed. A new transient clamp has been proposed to increase the power supply noise isolation. Finally, a new methodology of placement of analog circuit with respect to transient clamp has been proposed to further increase the power supply noise isolation

Hot carrier degradation in deep submicron n-MOS technologies

With the aggressive scaling of MOS devices hot carrier degradation continues to be a major reliability concern. The LDD technologies, which have been used to minimise the hot carrier damage in MOS devices, suffer from the spacer damage causing the drain series resistance degradation, along with the channel mobility degradation. Therefore, in order to optimise the performance and reliability of these technologies it is necessary to quantify the roles of spacer and channel damages in determining their degradation behaviour. In this thesis the hot carrier degradation behaviour of different generations of graded drain (lightly doped, mildly doped and highly doped) n-MOS technologies, designed for 5V, 3V and 2V operation is investigated. The stress time beginning from microseconds is investigated to study how the damage initiates and evolves over time. A technology dependent two-stage degradation behaviour in the measured transconductance with an early stage deviating from conventionally observed power law behaviour is reported. A methodology based on conventional extraction procedure using the L-array method is first developed to analyse the drain series resistance and the mobility degradation. For 5V technologies the analysis of the damage using this methodology shows a two-stage drain series resistance degradation with early stage lasting about lOOms. However, it is seen that the conventional series resistance and mobility degradation methodology fails to satisfactorily predict degradation behaviour of 3V and 2V technologies, resulting in unphysical decreasing extracted series resistance. It is shown that after the hot carrier stress a change in the universal mobility behaviour for channel lengths approaching quarter micron regime has a significant effect on the parameter extraction. A modified universal mobility model incorporating the effect of the interface charge is developed using the FN stress experiments. A new generalised extraction methodology modelling hot carrier stressed device as series combination of undamaged and damaged channel regions, along with the series source drain resistance is developed, incorporating the modified universal model in the damaged channel region. The new methodology has the advantage of being single device based and serves as an effective tool in evaluating. the roles of series resistance and mobility degradations for technology qualification. This is especially true for the deep submicron regime where the conventional extraction procedures are not applicable. Further, the new extraction method has the potential of being integrated into commercial device simulation tools, to accurately analyse the device degradation behaviour in deep submicron regime

Voltage sensing based built-in current sensor for IDDQ test

Quiescent current leakage test of the VDD supply (IDDQ Test) has been proven an effective way to screen out defective chips in manufacturing of Integrated Circuits (IC). As technology advances, the traditional IDDQ test is facing more and more challenges. In this research, a practical built-in current sensor (BICS) is proposed and the design is verified by three generations of test chips. The BICS detects the signal by sensing the voltage drop on supply lines of the circuit under test (CUT). Then the sensor performs analog-to-digital conversion of the input signal using a stochastic process with scan chain readout. Self-calibration and digital chopping are used to minimize offset and low frequency noise and drift. This non-invasive procedure avoids any performance degradation of the CUT. The measurement results of test chips are presented. The sensor achieves a high IDDQ resolution with small chip area overhead. This will enable IDDQ of future technology generations

Study Of Nanoscale Cmos Device And Circuit Reliability

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices from device level to circuit level; The more real voltage stress case high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future

Advanced modelling and design considerations for interconnects in ultra- low power digital system

PhD ThesisAs Very Large Scale Integration (VLSI) is progressing in very Deep submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption for advanced System-on- Chip (SoC)s. However, the growing complexity of interconnects behaviour presents a challenge for their adequate modelling, whereby conventional circuit theoretic approaches cannot provide sufficient accuracy. During the last decades, fractional differential calculus has been successfully applied to modelling certain classes of dynamical systems while keeping complexity of the models under acceptable bounds. For example, fractional calculus can help capturing inherent physical effects in electrical networks in a compact form, without following conventional assumptions about linearization of non-linear interconnect components. This thesis tackles the problem of interconnect modelling in its generality to simulate a wide range of interconnection configurations, its capacity to emulate irregular circuit elements and its simplicity in the form of responsible approximation. This includes modelling and analysing interconnections considering their irregular components to add more flexibility and freedom for design. The aim is to achieve the simplest adaptable model with the highest possible accuracy. Thus, the proposed model can be used for fast computer simulation of interconnection behaviour. In addition, this thesis proposes a low power circuit for driving a global interconnect at voltages close to the noise level. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles. The major contributions of this thesis are twofold. Firstly, in order to address Ultra-Low Power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver’s ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumption. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single event upset (SEU)s, which are known to affect DSM circuits working under low voltages. Secondly, the CMOS circuit driving a distributed RLC load has been brought in its analysis into the fractional order domain. This model will make the on-chip interconnect structure easy to adjust by including the effect of fractional orders on the interconnect timing, which has not been considered before. A second-order model for the transfer functions of the proposed general structure is derived, keeping the complexity associated with second-order models for this class of circuits at a minimum. The approach here attaches an important trait of robustness to the circuit design procedure; namely, by simply adjusting the fractional order we can avoid modifying the circuit components. This can also be used to optimise the estimation of the system’s delay for a broad range of frequencies, particularly at the beginning of the design flow, when computational speed is of paramount importance.Iraqi Ministry of Higher Education and Scientific Researc

Circuit designs for low-power and SEU-hardened systems

The desire to have smaller and faster portable devices is one of the primary motivations for technology scaling. Though advancements in device physics are moving at a very good pace, they might not be aggressive enough for now-a-day technology scaling trends. As a result, the MOS devices used for present day integrated circuits are pushed to the limit in terms of performance, power consumption and robustness, which are the most critical criteria for almost all applications. Secondly, technology advancements have led to design of complex chips with increasing chip densities and higher operating speeds. The design of such high performance complex chips (microprocessors, digital signal processors, etc) has massively increased the power dissipation and, as a result, the operating temperatures of these integrated circuits. In addition, due to the aggressive technology scaling the heat withstanding capabilities of the circuits is reducing, thereby increasing the cost of packaging and heat sink units. This led to the increase in prominence for smarter and more robust low-power circuit and system designs. Apart from power consumption, another criterion affected by technology scaling is robustness of the design, particularly for critical applications (security, medical, finance, etc). Thus, the need for error free or error immune designs. Until recently, radiation effects were a major concern in space applications only. With technology scaling reaching nanometer level, terrestrial radiation has become a growing concern. As a result Single Event Upsets (SEUs) have become a major challenge to robust designs. Single event upset is a temporary change in the state of a device due to a particle strike (usually from the radiation belts or from cosmic rays) which may manifest as an error at the output. This thesis proposes a novel method for adaptive digital designs to efficiently work with the lowest possible power consumption. This new technique improves options in performance, robustness and power. The thesis also proposes a new dual data rate flipflop, which reduces the necessary clock speed by half, drastically reducing the power consumption. This new dual data rate flip-flop design culminates in a proposed unique radiation hardened dual data rate flip-flop, Firebird\u27. Firebird offers a valuable addition to the future circuit designs, especially with the increasing importance of the Single Event Upsets (SEUs) and power dissipation with technology scaling.\u2

Integrated circuit outlier identification by multiple parameter correlation

Semiconductor manufacturers must ensure that chips conform to their specifications before they are shipped to customers. This is achieved by testing various parameters of a chip to determine whether it is defective or not. Separating defective chips from fault-free ones is relatively straightforward for functional or other Boolean tests that produce a go/no-go type of result. However, making this distinction is extremely challenging for parametric tests. Owing to continuous distributions of parameters, any pass/fail threshold results in yield loss and/or test escapes. The continuous advances in process technology, increased process variations and inaccurate fault models all make this even worse. The pass/fail thresholds for such tests are usually set using prior experience or by a combination of visual inspection and engineering judgment. Many chips have parameters that exceed certain thresholds but pass Boolean tests. Owing to the imperfect nature of tests, to determine whether these chips (called "outliers") are indeed defective is nontrivial. To avoid wasted investment in packaging or further testing it is important to screen defective chips early in a test flow. Moreover, if seemingly strange behavior of outlier chips can be explained with the help of certain process parameters or by correlating additional test data, such chips can be retained in the test flow before they are proved to be fatally flawed. In this research, we investigate several methods to identify true outliers (defective chips, or chips that lead to functional failure) from apparent outliers (seemingly defective, but fault-free chips). The outlier identification methods in this research primarily rely on wafer-level spatial correlation, but also use additional test parameters. These methods are evaluated and validated using industrial test data. The potential of these methods to reduce burn-in is discussed

Energy Efficient Design for Deep Sub-micron CMOS VLSIs

Over the past decade, low power, energy efficient VLSI design has been the focal point of active research and development. The rapid technology scaling, the growing integration capacity, and the mounting active and leakage power dissipation are contributing to the growing complexity of modern VLSI design. Careful power planning on all design levels is required. This dissertation tackles the low-power, low-energy challenges in deep sub-micron technologies on the architecture and circuit levels. Voltage scaling is one of the most efficient ways for reducing power and energy. For ultra-low voltage operation, a new circuit technique which allows bulk CMOS circuits to work in the sub-0. 5V supply territory is presented. The threshold voltage of the slow PMOS transistor is controlled dynamically to get a lower threshold voltage during the active mode. Due to the reduced threshold voltage, switching speed becomes faster while active leakage current is increased. A technique to dynamically manage active leakage current is presented. Energy reduction resulting from using the proposed structure is demonstrated through simulations of different circuits with different levels of complexity. As technology scales, the mounting leakage current and degraded noise immunity impact performance especially that of high performance dynamic circuits. Dual threshold technology shows a good potential for leakage reduction while meeting performance goals. A model for optimally selecting threshold voltages and transistor sizes in wide fan-in dynamic circuits is presented. On the circuit level, a novel circuit level technique which handles the trade-off between noise immunity and energy dissipation for wide fan-in dynamic circuits is presented. Energy efficiency of the proposed wide fan-in dynamic circuit is further enhanced through efficient low voltage operation. Another direct consequence of technology scaling is the growing impact of interconnect parasitics and process variations on performance. Traditionally, worst case process, parasitics, and environmental conditions are considered. Designing for worst case guarantees a fail-safe operation but requires a large delay and voltage margins. This large margin can be recovered if the design can adapt to the actual silicon conditions. Dynamic voltage scaling is considered a key enabler in reducing such margin. An on-chip process identifier to recover the margin required due to process variations is described. The proposed architecture adjusts supply voltage using a hybrid between the one-time voltage setting and the continuous monitoring modes of operation. The interconnect impact on delay is minimized through a novel adaptive voltage scaling architecture. The proposed system recovers the large delay and voltage margins required by conventional systems by closely tracking the actual critical path at anytime. By tracking the actual critical path, the proposed system is robust and more energy efficient compared to both the conventional open-loop and closed-loop systems