The characterization of recycled concrete aggregate as filter in removal of phosphorus

Phosphorus (P) is one of the key nutrients that lead to eutrophication problem in surface water. However, the existing conventional wastewater treatment system to remove phosphorus is expensive and require a complex process. Therefore, a system using low cost and environmental friendly should be practiced to overcome this problem. Recycled concrete aggregate (RCA) used as a filter system emerged as an alternative technology for phosphorus removal. This can overcome the problem of construction site waste by converting the waste into something valuable products. Thus, this study aim to investigate the physical and chemical characteristic of RCA that influenced adsorption of P. RCA was analyzed using Scanning Electron Microscopy (SEM) and Energy-dispersive X-ray spectroscopy (EDX) testing to determine chemical composition. Results shows that RCA is highly contained with Aluminium, Calcium and Magnesium elements that enhanced the Phosphorus adsorption

Design of a fault tolerant airborne digital computer. Volume 2: Computational requirements and technology

This final report summarizes the work on the design of a fault tolerant digital computer for aircraft. Volume 2 is composed of two parts. Part 1 is concerned with the computational requirements associated with an advanced commercial aircraft. Part 2 reviews the technology that will be available for the implementation of the computer in the 1975-1985 period. With regard to the computation task 26 computations have been categorized according to computational load, memory requirements, criticality, permitted down-time, and the need to save data in order to effect a roll-back. The technology part stresses the impact of large scale integration (LSI) on the realization of logic and memory. Also considered was module interconnection possibilities so as to minimize fault propagation

Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level

This paper presents utility for the design of the cross-coupled charge pump, which is used for supplying peripherals with low current consumption on the chip, as the EEPROM or FLASH memories. The article summarizes the knowledge in the field of the theoretical and practical analysis of the cross-coupled charge pump (design relationships and their connection with the pump parameters, as the threshold voltage, power supply voltage, clock signal frequency, etc.) that are applicated in the design algorithm. Optimal MOSFETs sizes (W, L) were find based on the construct of the time response characteristics of the pump sub-block and finding of the maximal voltage increase in the active interval of the clock signal and minimizing of the pump losses, as the switch reverse current, inverter cross current, etc. Synthesis process includes the design of the pump functional blocks with dominant real properties, which are described based on BSIM equations for long channel MOSFET. The pump stage complex model is applicated for estimation of the number of pump stages via state-space model description and using of the interpolation polynomial functions in the algorithm. It involves the construction of the time response characteristic due to the state variables and prediction of the number of the pump stages for the next cycle based on the previous data. Optimization of the pump area is based on the minimizing of the main capacitor in each of the pump stages (number of the pump stages must be increased to obtain the desired output voltage value.) Access is designed to stress the maximum pump voltage efficiency. The whole procedure is summarized in the practical example, in which the solution is shown both in terms of maximal voltage efficiency and the optimal pump area on a chip with respect to the clock signal frequency. Added functions of the design environment are explained, inclusive of the designed pump netlist generating for professional design environment Mentor Graphics including the real models of components that are available in library MGC Design Kit. The procedure gives designer credible results without long timeconsuming optimization process. In addition, the complex model allows the inclusion effects of higher-levels

Computing centroids in current-mode technique

A novel current-mode circuit for calculating the centre of mass of a discrete distribution of currents is described. It is simple and compact, an ideal building block for VLSI analogue IC design. The design principles are presented as well as the simulated behaviour of a one-dimensional implementation

A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors

This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.Comisión Interministerial de Ciencia y Tecnología TIC96- 1392-C02-0

System and component design and test of a 10 hp, 18,000 rpm AC dynamometer utilizing a high frequency AC voltage link, part 1

Hard and soft switching test results conducted with one of the samples of first generation MOS-controlled thyristor (MCTs) and similar test results with several different samples of second generation MCT's are reported. A simple chopper circuit is used to investigate the basic switching characteristics of MCT under hard switching and various types of resonant circuits are used to determine soft switching characteristics of MCT under both zero voltage and zero current switching. Next, operation principles of a pulse density modulated converter (PDMC) for three phase (3F) to 3F two-step power conversion via parallel resonant high frequency (HF) AC link are reviewed. The details for the selection of power switches and other power components required for the construction of the power circuit for the second generation 3F to 3F converter system are discussed. The problems encountered in the first generation system are considered. Design and performance of the first generation 3F to 3F power converter system and field oriented induction moter drive based upon a 3 kVA, 20 kHz parallel resonant HF AC link are described. Low harmonic current at the input and output, unity power factor operation of input, and bidirectional flow capability of the system are shown via both computer and experimental results. The work completed on the construction and testing of the second generation converter and field oriented induction motor drive based upon specifications for a 10 hp squirrel cage dynamometer and a 20 kHz parallel resonant HF AC link is discussed. The induction machine is designed to deliver 10 hp or 7.46 kW when operated as an AC-dynamo with power fed back to the source through the converter. Results presented reveal that the proposed power level requires additional energy storage elements to overcome difficulties with a peak link voltage variation problem that limits reaching to the desired power level. The power level test of the second generation converter after the addition of extra energy storage elements to the HF link are described. The importance of the source voltage level to achieve a better current regulation for the source side PDMC is also briefly discussed. The power levels achieved in the motoring mode of operation show that the proposed power levels achieved in the generating mode of operation can also be easily achieved provided that no mechanical speed limitation were present to drive the induction machine at the proposed power level