Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Modeling and Fabrication of Low Power Devices and Circuits Using Low-Dimensional Materials

University of Minnesota Ph.D. dissertation.July 2016. Major: Electrical Engineering. Advisor: Steven Koester. 1 computer file (PDF); x, 112 pages.As silicon approaches its ultimate scaling limit as a channel material for conventional semiconductor devices, alternate mechanisms and materials are emerging rapidly to replace or complement conventional silicon based devices. Attractive semiconducting properties such as high mobility, excellent interface quality, and better scalability are the properties desired for materials to be explored for electronic and photonic device applications. Hybrid III-V semiconductor based tunneling field effect transistors (TFETs) can provide a strong alternative due to their attractive properties such as subthreshold slopes less than 60 mV/decade, which can lead to aggressive power supply scaling. Here, InAs-SiGe-Si based TFETs are studied in detail. Simulations predict that subthreshold slopes as low as 18 mV/decade and on currents as high as 50 µA/µm can be achieved using such a device. However, the simulations also show that the device performance is limited by (1) the low density of states in the source which induces a trade-off between the source doping and the subthreshold slope, limiting power supply scaling, and (2) direct source-to-drain tunneling which limits gate length scaling. Another approach to explore low power alternatives to conventional semiconductor device can be to use emerging two-dimensional (2D) materials. In particular, the transition metal dichalcogenides (TMDs) are promising material group that, like graphene, these material exhibit 2D nature, but unlike graphene, have a finite band gap. In this work, the off-state characteristics are modelled for MoS2 MOSFETs (metal–oxide–semiconductor field-effect transistors), and their circuit performance is predicted. MoS2 Due to its higher effective masses and large band gap compared to silicon it is shown that MoS2 MOSFETs are well suited for dynamic memory applications. Two of such circuits, one transistor one capacitor (1TIC) and two transistor (2T) dynamic memory cells have been fabricated for the first time. Retention times as high as 0.25 second and 1.3 second for the 1T1C and 2T cell, respectively, are demonstrated. Moreover, ultra-low leakage currents less than femto-ampere per micron are extracted based on the retention time measurements. These results establish the potential of 2D MoS2 as an attractive material for low power device and circuit applications

Silicon Nanodevices

This book is a collection of scientific articles which brings research in Si nanodevices, device processing, and materials. The content is oriented to optoelectronics with a core in electronics and photonics. The issue of current technology developments in the nanodevices towards 3D integration and an emerging of the electronics and photonics as an ultimate goal in nanotechnology in the future is presented. The book contains a few review articles to update the knowledge in Si-based devices and followed by processing of advanced nano-scale transistors. Furthermore, material growth and manufacturing of several types of devices are presented. The subjects are carefully chosen to critically cover the scientific issues for scientists and doctoral students

Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications