A new Version of High Stability Output 12-Bit Tracking Analog to Digital Converter

    In this paper a 12-bit tracking analog-to-digital converter (ADC) is designed and its performance is verified. It continuously tests the analog input signal and makes correction when necessary. The resulting digital equivalent of the analog input signal is continuously updated. The least significant bit (LSB) of this converter jumps up and down to track the analog input and this causes the final output to be unstable. To overcome the problem of instability in the digital output the 12-bit tracking ADC is modified by introducing the test bit B0. The test bit is designed to have a voltage equals to that of the LSB. It always sets or resets in tracking the analog value. Using this technique the digital output B1 to B12 of the converter is maintained stable. Test and measurements are performed in the converter circuit to demonstrate the practicality of this version.              &nbsp

Adaptive non-uniform photonic time stretch for blind RF signal detection with compressed time-bandwidth product

Photonic time stretch significantly extends the effective bandwidth of existing analog-to-digital convertors by slowing down the input high-speed RF signals. Non-uniform photonic time stretch further enables time bandwidth product reduction in RF signal detection by selectively stretching high-frequency features more. However, it requires the prior knowledge of spectral-temporal distribution of the input RF signal and has to reconfigure the time stretch filter for different RF input signals. Here we propose for the first time an adaptive non-uniform photonic time stretch method based on microwave photonics pre-stretching that achieves blind detection of high-speed RF signals with reduced time bandwidth product. Non-uniform photonic time stretch using both quadratic and cubic group delay response has been demonstrated and time bandwidth product compression ratios of 72% and 56% have been achieved respectively

Performance of serial time-encoded amplified microscope

Serial time-encoded amplified microscopy (STEAM) is an entirely new imaging modality that enables ultrafast continuous real-time imaging with high sensitivity. By means of optical image amplification, STEAM overcomes the fundamental tradeoff between sensitivity and speed that affects virtually all optical imaging systems. Unlike the conventional microscope systems, the performance of STEAM depends not only on the lenses, but also on the properties of other components that are unique to STEAM, namely the spatial disperser, the group velocity dispersion element, and the back-end electronic digitizer. In this paper, we present an analysis that shows how these considerations affect the spatial resolution, and how they create a trade-off between the number of pixels and the frame rate of the STEAM imager. We also quantify how STEAM's optical image amplification feature improves the imaging sensitivity. These analyses not only provide valuable insight into the operation of STEAM technology but also serve as a blue print for implementation and optimization of this new imaging technology. ©2010 Optical Society of America.published_or_final_versio

A jittered-sampling correction technique for ADCs

In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied

A locally-adaptive imager

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 149-154).by Pablo M. Acosta Serafini.M.S

Fully-photonic digital radio over fibre for future super-broadband access network applications

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel UniversityIn this thesis a Fully-Photonic DRoF (FP-DRoF) system is proposed for deploying of future super-broadband access networks. Digital Radio over Fibre (DRoF) is more independent of the fibre network impairments and the length of fibre than the ARoF link. In order for fully optical deployment of the signal conversion techniques in the FP-DRoF architecture, two key components an Analogue-to-Digital Converter (ADC) and a Digital-to-Analogue Converter (DAC)) for data conversion are designed and their performance are investigated whereas the physical functionality is evaluated. The system simulation results of the proposed pipelined Photonic ADC (PADC) show that the PADC has 10 GHz bandwidth around 60 GHz of sampling rate. Furthermore, by changing the bandwidth of the optical bandpass filter, switching to another band of sampling frequency provides optimised performance condition of the PADC. The PADC has low changes on the Effective Number of Bit (ENOB) response versus analogue RF input from 1 GHz up to 22 GHz for 60 GHz sampling frequency. The proposed 8-Bit pipelined PADC performance in terms of ENOB is evaluated at 60 Gigasample/s which is about 4.1. Recently, different methods have been reported by researchers to implement Photonic DACs (PDACs), but their aim was to convert digital electrical signals to the corresponding analogue signal by assisting the optical techniques. In this thesis, a Binary Weighted PDAC (BW-PDAC) is proposed. In this BW-PDAC, optical digital signals are fully optically converted to an analogue signal. The spurious free dynamic range at the output of the PDAC in a back-to-back deployment of the PADC and the PDAC was 26.6 dBc. For further improvement in the system performance, a 3R (Retiming, Reshaping and Reamplifying) regeneration system is proposed in this thesis. Simulation results show that for an ultrashort RZ pulse with a 5% duty cycle at 65 Gbit/s using the proposed 3R regeneration system on a link reduces rms timing jitter by 90% while the regenerated pulse eye opening height is improved by 65%. Finally, in this thesis the proposed FP-DRoF functionality is evaluated whereas its performance is investigated through a dedicated and shared fibre links. The simulation results show (in the case of low level signal to noise ratio, in comparison with ARoF through a dedicated fibre link) that the FP-DRoF has better BER performance than the ARoF in the order of 10-20. Furthermore, in order to realize a BER about 10-25 for the ARoF, the power penalty is about 4 dBm higher than the FP-DRoF link. The simulation results demonstrate that by considering 0.2 dB/km attenuation of a standard single mode fibre, the dedicated fibre length for the FP-DRoF link can be increased to about 20 km more than the ARoF link. Moreover, for performance assessment of the proposed FP-DRoF in a shared fibre link, the BER of the FP-DRoF link is about 10-10 magnitude less than the ARoF link for -19 dBm launched power into the fibre and the power penalty of the ARoF system is 10 dBm more than the FP-DRoF link. It is significant to increase the fibre link’s length of the FP-DRoF access network using common infrastructure. In addition, the simulation results are demonstrated that the FP-DRoF with non-uniform Wavelength Division Multiplexing (WDM) is more robust against four wave mixing impairment than the conventional WDM technique with uniform wavelength allocation and has better performance in terms of BER. It is clearly verified that the lunched power penalty at CS for DRoF link with uniform WDM techniques is about 2 dB higher than non-uniform WDM technique. Furthermore, uniform WDM method requires more bandwidth than non-uniform scheme which depends on the total number of channels and channels spacing

Fault tolerant programmable digital attitude control electronics study

The attitude control electronics mechanization study to develop a fault tolerant autonomous concept for a three axis system is reported. Programmable digital electronics are compared to general purpose digital computers. The requirements, constraints, and tradeoffs are discussed. It is concluded that: (1) general fault tolerance can be achieved relatively economically, (2) recovery times of less than one second can be obtained, (3) the number of faulty behavior patterns must be limited, and (4) adjoined processes are the best indicators of faulty operation

Design, analysis and implementation of voltage sensor for power-constrained systems

PhD ThesisThanks to an extensive effort by the global research community, the electronic technology has significantly matured over the last decade. This technology has enabled certain operations which humans could not otherwise easily perform. For instance, electronic systems can be used to perform sensing, monitoring and even control operations in environments such as outer space, underground, under the sea or even inside the human body. The main difficulty for electronics operating in these environments is access to a reliable and permanent source of energy. Using batteries as the immediate solution for this problem has helped to provide energy for limited periods of time; however, regular maintenance and replacement are required. Consequently, battery solutions fail wherever replacing them is not possible or operation for long periods is needed. For such cases, researchers have proposed harvesting ambient energy and converting it into an electrical form. An important issue with energy harvesters is that their operation and output power depend critically on the amount of energy they receive and because ambient energy often tends to be sporadic in nature, energy harvesters cannot produce stable or fixed levels of power all of the time. Therefore, electronic devices powered in this way must be capable of adapting their operation to the energy status of the harvester. To achieve this, information on the energy available for use is needed. This can be provided by a sensor capable of measuring voltage. However, stable and fixed voltage and time references are a prerequisite of most traditional voltage measurement devices, but these generally do not exist in energy harvesting environments. A further challenge is that such a sensor also needs to be powered by the energy harvester’s unstable voltage. In this thesis, the design of a reference-free voltage sensor, which can operate with a varying voltage source, is provided based on the capture of a portion of the total energy which is directly related to II the energy being sensed. This energy is then used to power a computation which quantifies captured energy over time, with the information directly generated as digital code. The sensor was fabricated in the 180 nm technology node and successfully tested by performing voltage measurements over the range 1.8 V to 0.8 V