Mobile Robot Online Motion Planning Using Generalized Voronoi Graphs

In this paper, a new online robot motion planner is developed for systematically exploring unknown environ¬ments by intelligent mobile robots in real-time applications. The algorithm takes advantage of sensory data to find an obstacle-free start-to-goal path. It does so by online calculation of the Generalized Voronoi Graph (GVG) of the free space, and utilizing a combination of depth-first and breadth-first searches on the GVG. The planner is equipped with components such as step generation and correction, backtracking, and loop handling. It is fast, simple, complete, and extendable to higher spaces

Feature-based hybrid inspection planning for complex mechanical parts

Globalization and emerging new powers in the manufacturing world are among many challenges, major manufacturing enterprises are facing. This resulted in increased alternatives to satisfy customers\u27 growing needs regarding products\u27 aesthetic and functional requirements. Complexity of part design and engineering specifications to satisfy such needs often require a better use of advanced and more accurate tools to achieve good quality. Inspection is a crucial manufacturing function that should be further improved to cope with such challenges. Intelligent planning for inspection of parts with complex geometric shapes and free form surfaces using contact or non-contact devices is still a major challenge. Research in segmentation and localization techniques should also enable inspection systems to utilize modern measurement technologies capable of collecting huge number of measured points. Advanced digitization tools can be classified as contact or non-contact sensors. The purpose of this thesis is to develop a hybrid inspection planning system that benefits from the advantages of both techniques. Moreover, the minimization of deviation of measured part from the original CAD model is not the only characteristic that should be considered when implementing the localization process in order to accept or reject the part; geometric tolerances must also be considered. A segmentation technique that deals directly with the individual points is a necessary step in the developed inspection system, where the output is the actual measured points, not a tessellated model as commonly implemented by current segmentation tools. The contribution of this work is three folds. First, a knowledge-based system was developed for selecting the most suitable sensor using an inspection-specific features taxonomy in form of a 3D Matrix where each cell includes the corresponding knowledge rules and generate inspection tasks. A Travel Salesperson Problem (TSP) has been applied for sequencing these hybrid inspection tasks. A novel region-based segmentation algorithm was developed which deals directly with the measured point cloud and generates sub-point clouds, each of which represents a feature to be inspected and includes the original measured points. Finally, a new tolerance-based localization algorithm was developed to verify the functional requirements and was applied and tested using form tolerance specifications. This research enhances the existing inspection planning systems for complex mechanical parts with a hybrid inspection planning model. The main benefits of the developed segmentation and tolerance-based localization algorithms are the improvement of inspection decisions in order not to reject good parts that would have otherwise been rejected due to misleading results from currently available localization techniques. The better and more accurate inspection decisions achieved will lead to less scrap, which, in turn, will reduce the product cost and improve the company potential in the market

ReSCon '09, Research Student Conference: Book of Abstracts

The second SED Research Student Conference (ReSCon2009) was hosted over three days, 22-24 June 2009, in the Lecture Centre at Brunel University. The conference consisted of technical presentations, a poster session and social events. The abstracts and presentations were the result of ongoing research by postgraduate research students from the School of Engineering and Design at Brunel University. The conference is held annually, and ReSCon plays a key role in contributing to research and innovations within the School

Digital Library Services for Three-Dimensional Models

With the growth in computing, storage and networking infrastructure, it is becoming increasingly feasible for multimedia professionals—such as graphic designers in commercial, manufacturing, scientific and entertainment areas—to work with 3D digital models of the objects with which they deal in their domain. Unfortunately most of these models exist in individual repositories, and are not accessible to geographically distributed professionals who are in need of them. Building an efficient digital library system presents a number of challenges. In particular, the following issues need to be addressed: (1) What is the best way of representing 3D models in a digital library, so that the searches can be done faster? (2) How to compress and deliver the 3D models to reduce the storage and bandwidth requirements? (3) How can we represent the user\u27s view on similarity between two objects? (4) What search types can be used to enhance the usability of the digital library and how can we implement these searches, what are the trade-offs? In this research, we have developed a digital library architecture for 3D models that addresses the above issues as well as other technical issues. We have developed a prototype for our 3D digital library (3DLIB) that supports compressed storage, along with retrieval of 3D models. The prototype also supports search and discovery services that are targeted for 3-D models. The key to 3DLIB is a representation of a 3D model that is based on “surface signatures”. This representation captures the shape information of any free-form surface and encodes it into a set of 2D images. We have developed a shape similarity search technique that uses the signature images to compare 3D models. One advantage of the proposed technique is that it works in the compressed domain, thus it eliminates the need for uncompressing in content-based search. Moreover, we have developed an efficient discovery service consisting of a multi-level hierarchical browsing service that enables users to navigate large sets of 3D models. To implement this targeted browsing (find an object that is similar to a given object in a large collection through browsing) we abstract a large set of 3D models to a small set of representative models (key models). The abstraction is based on shape similarity and uses specially tailored clustering techniques. The browsing service applies clustering recursively to limit the number of key models that a user views at any time. We have evaluated the performance of our digital library services using the Princeton Shape Benchmark (PSB) and it shows significantly better precision and recall, as compared to other approaches

Design-Informed Generative Modelling using Structural Optimization

Although various structural optimization techniques have a sound mathematical basis, the practical constructability of optimal designs poses a great challenge in the manufacturing stage. Currently, there is only a limited number of unified frameworks which output ready-to-manufacture parametric Computer-Aided Designs (CAD) of the optimal designs. From a generative design perspective, it is essential to have a single platform that outputs a structurally optimized CAD model because CAD models are an integral part of most industrial product development and manufacturing stages. This study focuses on developing a novel unified workflow handling topology, layout and size optimization in a single parametric platform, which subsequently outputs a ready-to-manufacture CAD model. All such outputs are checked and validated for structural requirements; strength, stiffness and stability in accordance with standard codes of practice. In the proposed method, first, topology-optimal model is generated and converted to a one-pixel-wide chain model using skeletonization. Secondly, a spatial frame is extracted from the skeleton for its member size and layout optimization. Finally, the CAD model is generated using constructive solid geometry trees and the structural integrity of each member is assessed to ensure structural robustness prior to manufacturing. Various examples presented in the paper showcase the validity of the proposed method across various engineering disciplines

Rapid manufacturing of vacuum forming components utilising reconfigurable screw pin tooling

Current market trends are moving from large quantity production towards small batch production and mass customization. This has led to the high demand for the flexibility and adaptability of manufacturing technology and systems. Several reconfigurable pin type tooling systems have been proposed and developed to satisfy such demands. However, these reconfigurable tooling systems still suffer from several drawbacks, including difficulties associated with positioning and locking the pins and problems of uneven “staircase” surface effects from relying on discrete finite size pins. The main focus of this research is on building a hybrid vacuum-forming machine system (HAVES) based on reconfigurable screw-pin tooling (SPT)as a test bed for understanding the processes involved in developing this technology and to examine the feasibility of implementing such technology in an industrial system. The SPT used is composed of identical screw pins,which are engaged with each other in an array pattern. By adjusting vertical displacement of the screw pins, a wide variety of component geometry can be formed. The adjustment methodology of the SPT is formulated mathematically in order to help construction of the SPT be parametrical thus enabling automatic CNC G-code generation. The HAVES test bed development involves full machine design and hardware and software integration. The hardware integration task included a CNC controller, drive motors, encoders, milling and screw adjustment heads, SPT, vacuum forming system. The software integration task involved the processing of three-dimensional CAD geometry to automatically generate post processed G codes in order to adjust the screw-pin to the required component geometry and subsequent surface machining for driving the final die geometry and minimize operator intervention. The completed HAVES test bed has been tested for accuracy, repeatability and functionalities with quality good results. An economic analysis has been also conducted to verify the economic feasibility of the HAVES test bed by comparing the cost of making vacuum forming components using a dedicated mould versus using the HAVES test bed

Design of Special Function Units in Modern Microprocessors

Today’s computing systems demand high performance for applications such as cloud computing, web-based search engines, network applications, and social media tasks. Such software applications involve an extensive use of hashing and arithmetic operations in their computation. In this thesis, we explore the use of new special function units (SFUs) for modern microprocessors, to accelerate such workloads. First, we design an SFU for hashing. Hashing can reduce the complexity of search and lookup from O(p) to O(p/n), where n bins are used and p items are being processed. In modern microprocessors, hashing is done in software. In our work, we propose a novel hardware hash unit design for use in modern microprocessors. Since the hash unit is designed at the hardware level, several advantages are obtained by our approach. First, a hardware-based hash unit executes a single hash instruction to perform a hash operation. In a software-based hashing in modern microprocessors, a hash operation is compiled into multiple instructions, thereby degrading performance. Second, software-based hashing stores hash data in a DRAM (also, hash operation entries can be stored in one of the cache levels). In a hardware-based hash unit, hash data is stored in a dedicated memory module (a hardware hash table), which improves performance. Third, today’s operating systems execute multiple applications (processes) in parallel, which entail high memory utilization. Hence the operating systems require many context switching between different processes, which results in many cache misses. In a hardware-based hash unit, the cache misses is reduced significantly using the dedicated memory module (hash table). These advantages all reduce the power consumption and increase the overall system performance significantly with a minimal increase in the microprocessor’s die area. We evaluate our hardware-based hash unit and compare its performance with software-based hashing. We start by evaluating our design approach at the micro-architecture level in terms of system performance. After that, we design our approach at the circuit level design to obtain the area overhead. Also, we analyze our design’s power and delay for each hash operation. These results are compared with a traditional hashing implementation. Then, we present an FPGA-based coprocessor for hash unit acceleration, applied to a virus checking application. Second, we present an SFU to speed up arithmetic operations. We call this arithmetic SFU a programmable arithmetic unit (PAU). In modern microprocessors, applications that require heavy arithmetic computations are done in software. To improve the performance for such computations, we present a programmable arithmetic unit (PAU), a partially reconfigurable methodology for arithmetic applications. The PAU consists of a set of IP blocks connected to a reconfigurable FPGA controller via a fast mesh-based interconnect. The IP blocks in the PAU can be any IP block such as adders, subtractors, multipliers, comparators and sign extension units. The PAU can have one or more copies of the same IP block (for example, 5 adders and 7 multipliers). The FPGA controller is an on-chip FPGA-based reconfigurable control fabric. The FPGA controller enables different arithmetic applications to be embedded on the PAU. The FPGA controller is programmed for different applications. The reconfigurable logic is based on a LUT-based design like a traditional FPGA. The FPGA controller and the IP blocks in the PAU communicate via a high speed ring data fabric. In our work, we use the PAU as an SFU in modern microprocessors. We compare the performance of different hardware-based arithmetic applications in the PAU with software-based implementations in modern microprocessors