Knowledge-based system for diagnosis of microprocessor system.

Yau Po Chung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 91-92).Abstract also in Chinese.Chapter 1 --- Introduction --- p.1Chapter 2 --- Background --- p.3Chapter 2.1 --- Temporal Theories --- p.3Chapter 2.2 --- Related Works --- p.4Chapter 2.2.1 --- Consistency and Satisfiability of Timing Specifications --- p.4Chapter 2.2.2 --- Symbolic Constraint Satisfaction --- p.5Chapter 3 --- Previous Developed Work --- p.7Chapter 3.1 --- Previous Problem Domain --- p.7Chapter 3.1.1 --- Basics of MC68000 Read Cycle --- p.7Chapter 3.2 --- Knowledge-based System Structure --- p.9Chapter 3.3 --- Diagnostic Reasoning Mechanisms --- p.10Chapter 3.4 --- Time Range Approach --- p.11Chapter 3.4.1 --- Time Range Representation --- p.11Chapter 3.4.2 --- Constraint Satisfaction of Time Ranges --- p.12Chapter 3.4.3 --- Constraint Propagation of Time Ranges --- p.13Chapter 3.5 --- Fuzzy Time Point Approach --- p.14Chapter 3.5.1 --- Fuzzy Time Point Models --- p.14Chapter 3.5.2 --- Definition of Fuzzy Time Points --- p.15Chapter 3.5.3 --- Constraint Propagation of Fuzzy Time Points --- p.17Chapter 3.5.4 --- Constraint Satisfaction of Fuzzy Time Points --- p.18Chapter 4 --- The Proposed Segmented Time Range Approach --- p.20Chapter 4.1 --- Introduction --- p.20Chapter 4.2 --- The Insufficiency of The Existing Time Range Approach --- p.22Chapter 4.3 --- Segmented Time Range Approach --- p.23Chapter 4.3.1 --- The Representation --- p.23Chapter 4.3.2 --- Constraint Propagation and Satisfaction --- p.25Chapter 4.3.3 --- Contributions --- p.25Chapter 4.3.4 --- Limitations --- p.29Chapter 4.4 --- Conclusion --- p.30Chapter 5 --- New Problem Domain and Our New System --- p.31Chapter 5.1 --- Introduction --- p.31Chapter 5.2 --- Pentium-SRAM Interfacing Problem --- p.31Chapter 5.2.1 --- Asynchronous SRAM Solution --- p.32Chapter 5.2.2 --- Synchronous SRAM Solution --- p.33Chapter 5.3 --- The Knowledge Base --- p.35Chapter 5.4 --- Characteristics of Our New System --- p.35Chapter 6 --- Burst Read Cycle --- p.37Chapter 6.1 --- Introduction --- p.37Chapter 6.2 --- Asynchronous SRAM Solution --- p.37Chapter 6.2.1 --- Implementation --- p.39Chapter 6.2.2 --- Implementation Results --- p.45Chapter 6.3 --- Synchronous SRAM Solution --- p.48Chapter 6.3.1 --- Implementation --- p.49Chapter 6.3.2 --- Implementation Results --- p.56Chapter 6.4 --- Conclusion --- p.58Chapter 7 --- Burst Write Cycle --- p.60Chapter 7.1 --- Introduction --- p.60Chapter 7.2 --- Asynchronous SRAM Solution --- p.60Chapter 7.2.1 --- Implementation --- p.61Chapter 7.2.2 --- Implementation Results --- p.67Chapter 7.3 --- Synchronous SRAM Solution --- p.71Chapter 7.3.1 --- Implementation --- p.71Chapter 7.3.2 --- Implementation Results --- p.79Chapter 7.4 --- Conclusion --- p.82Chapter 8 --- Conclusion --- p.83Chapter 8.1 --- Summary of Achievements --- p.83Chapter 8.2 --- Future Development --- p.86Appendix Some Characteristics of Our New System --- p.89Bibliography --- p.9

Temporal constraint reasoning in microprocessor systems diagnosis.

by Yuen Siu Ming.Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.Includes bibliographical references (leaves 104-110).Chapter 1 --- Introduction --- p.1Chapter 2 --- Background --- p.4Chapter 2.1 --- Approaches in Formal Hardware Verification --- p.4Chapter 2.1.1 --- Theorem Proving --- p.5Chapter 2.1.2 --- Symbolic Simulation --- p.5Chapter 2.1.3 --- Model Checking --- p.6Chapter 2.2 --- Temporal Theories --- p.7Chapter 2.3 --- Related Works --- p.8Chapter 2.3.1 --- Consistency and Satisfiability of Timing Specifications --- p.8Chapter 2.3.2 --- Symbolic Constraint Satisfaction --- p.9Chapter 3 --- Problem Domain --- p.11Chapter 3.1 --- Basics of MC68000 Read Cycle --- p.11Chapter 4 --- Knowledge-based System Structure --- p.13Chapter 4.1 --- Diagnostic Reasoning Mechanisms --- p.14Chapter 4.2 --- Occurring Event Sequence --- p.16Chapter 4.3 --- Equivalent Goals --- p.17Chapter 4.4 --- CPU Databus Setup Time --- p.17Chapter 4.5 --- Assertion of CPU AS Signal --- p.19Chapter 5 --- Time Range Approach --- p.21Chapter 5.1 --- Time Range Represent ation --- p.21Chapter 5.2 --- Time Ranges Reasoning Techniques --- p.22Chapter 5.2.1 --- Constraint Satisfaction of Time Ranges --- p.22Chapter 5.2.2 --- Constraint Propagation of Time Ranges --- p.25Chapter 5.3 --- Worst-Case Timing Analysis --- p.28Chapter 5.4 --- System Implementation --- p.29Chapter 5.4.1 --- CPU Databus Setup Time --- p.30Chapter 5.4.2 --- Assertion of CPU AS Signal --- p.36Chapter 5.5 --- Implementation Results --- p.40Chapter 5.5.1 --- CPU Databus Setup Time --- p.40Chapter 5.5.2 --- Assertion of CPU AS Signal --- p.40Chapter 5.6 --- Conclusion --- p.41Chapter 6 --- Fuzzy Time Point Approach --- p.43Chapter 6.1 --- Fuzzy Time Point Models --- p.44Chapter 6.1.1 --- Concept of Fuzzy Numbers --- p.44Chapter 6.1.2 --- Definition of Fuzzy Time Points --- p.45Chapter 6.1.3 --- Semi-bounded Fuzzy Time Points --- p.47Chapter 6.2 --- Fuzzy Time Point Reasoning Techniques --- p.48Chapter 6.2.1 --- Constraint Propagation of Fuzzy Time Points --- p.50Chapter 6.2.2 --- Constraint Satisfaction of Fuzzy Time Points --- p.52Chapter 6.3 --- System Implementation --- p.55Chapter 6.3.1 --- Representation of Fuzzy Time Point --- p.55Chapter 6.3.2 --- Fuzzy Time Point Satisfaction --- p.56Chapter 6.3.3 --- Fuzzy Time Point Propagation --- p.58Chapter 6.4 --- Implementation Results --- p.64Chapter 6.4.1 --- CPU Databus Setup Time --- p.64Chapter 6.4.2 --- Assertion of CPU AS Signal --- p.65Chapter 6.5 --- Fuzzy Time Point Model Parameters --- p.66Chapter 6.5.1 --- Variation of Semi-bounded ftps' Membership Function --- p.66Chapter 6.5.2 --- Variation of μftp --- p.67Chapter 6.5.3 --- Variation of K --- p.69Chapter 6.6 --- Conclusion --- p.69Chapter 7 --- Constraint Compatibility Reasoning --- p.72Chapter 7.1 --- Abstract Timing Parameters --- p.73Chapter 7.2 --- MC68000 Read Cycle: Wait States Insertion --- p.75Chapter 7.3 --- Constraint Compatibility of Fuzzy Time Point --- p.75Chapter 7.3.1 --- Crisp Threshold Value --- p.77Chapter 7.3.2 --- Possibility Quantification for the Number of Wait States --- p.78Chapter 7.3.3 --- Threshold Beyond Fuzzy Time Point --- p.80Chapter 7.3.4 --- Fuzzy Time Point Beyond Threshold --- p.80Chapter 7.3.5 --- Threshold Within Fuzzy Time Point --- p.82Chapter 7.4 --- Determine When CPU Clock State is S5 --- p.83Chapter 7.5 --- System Implementation --- p.84Chapter 7.5.1 --- Expert's Heuristic Rule --- p.84Chapter 7.5.2 --- Constraint Compatibility --- p.85Chapter 7.5.3 --- Wait States Insertion --- p.87Chapter 7.6 --- Implementation Results --- p.91Chapter 7.7 --- Conclusion --- p.93Chapter 8 --- Conclusion --- p.95Chapter 8.1 --- Applications in Other Domains --- p.97Chapter 8.2 --- Future Directions and Recommendations --- p.98Chapter A --- Constraint Compatibility Reasoning Output --- p.99Chapter A.1 --- No Wait Cycle Insertion --- p.99Chapter A.2 --- Single Wait Cycle Insertion --- p.100Chapter A.3 --- Two Wait Cycle Insertions --- p.100Chapter B --- MC68020 Read Cycle Problem --- p.101Chapter B.1 --- Basics of MC68020 Read Cycle --- p.101Chapter B.2 --- MC68020 Databus Setup Time --- p.102Chapter B.3 --- Implementation Results --- p.103Bibliography --- p.10

Approaches to the implementation of binary relation inference network.

by C.W. Tong.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.Includes bibliographical references (leaves 96-98).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- The Availability of Parallel Processing Machines --- p.2Chapter 1.1.1 --- Neural Networks --- p.5Chapter 1.2 --- Parallel Processing in the Continuous-Time Domain --- p.6Chapter 1.3 --- Binary Relation Inference Network --- p.10Chapter 2 --- Binary Relation Inference Network --- p.12Chapter 2.1 --- Binary Relation Inference Network --- p.12Chapter 2.1.1 --- Network Structure --- p.14Chapter 2.2 --- Shortest Path Problem --- p.17Chapter 2.2.1 --- Problem Statement --- p.17Chapter 2.2.2 --- A Binary Relation Inference Network Solution --- p.18Chapter 3 --- A Binary Relation Inference Network Prototype --- p.21Chapter 3.1 --- The Prototype --- p.22Chapter 3.1.1 --- The Network --- p.22Chapter 3.1.2 --- Computational Element --- p.22Chapter 3.1.3 --- Network Response Time --- p.27Chapter 3.2 --- Improving Response --- p.29Chapter 3.2.1 --- Removing Feedback --- p.29Chapter 3.2.2 --- Selecting Minimum with Diodes --- p.30Chapter 3.3 --- Speeding Up the Network Response --- p.33Chapter 3.4 --- Conclusion --- p.35Chapter 4 --- VLSI Building Blocks --- p.36Chapter 4.1 --- The Site --- p.37Chapter 4.2 --- The Unit --- p.40Chapter 4.2.1 --- A Minimum Finding Circuit --- p.40Chapter 4.2.2 --- A Tri-state Comparator --- p.44Chapter 4.3 --- The Computational Element --- p.45Chapter 4.3.1 --- Network Performances --- p.46Chapter 4.4 --- Discussion --- p.47Chapter 5 --- A VLSI Chip --- p.48Chapter 5.1 --- Spatial Configuration --- p.49Chapter 5.2 --- Layout --- p.50Chapter 5.2.1 --- Computational Elements --- p.50Chapter 5.2.2 --- The Network --- p.52Chapter 5.2.3 --- I/O Requirements --- p.53Chapter 5.2.4 --- Optional Modules --- p.53Chapter 5.3 --- A Scalable Design --- p.54Chapter 6 --- The Inverse Shortest Paths Problem --- p.57Chapter 6.1 --- Problem Statement --- p.59Chapter 6.2 --- The Embedded Approach --- p.63Chapter 6.2.1 --- The Formulation --- p.63Chapter 6.2.2 --- The Algorithm --- p.65Chapter 6.3 --- Implementation Results --- p.66Chapter 6.4 --- Other Implementations --- p.67Chapter 6.4.1 --- Sequential Machine --- p.67Chapter 6.4.2 --- Parallel Machine --- p.68Chapter 6.5 --- Discussion --- p.68Chapter 7 --- Closed Semiring Optimization Circuits --- p.71Chapter 7.1 --- Transitive Closure Problem --- p.72Chapter 7.1.1 --- Problem Statement --- p.72Chapter 7.1.2 --- Inference Network Solutions --- p.73Chapter 7.2 --- Closed Semirings --- p.76Chapter 7.3 --- Closed Semirings and the Binary Relation Inference Network --- p.79Chapter 7.3.1 --- Minimum Spanning Tree --- p.80Chapter 7.3.2 --- VLSI Implementation --- p.84Chapter 7.4 --- Conclusion --- p.86Chapter 8 --- Conclusions --- p.87Chapter 8.1 --- Summary of Achievements --- p.87Chapter 8.2 --- Future Work --- p.89Chapter 8.2.1 --- VLSI Fabrication --- p.89Chapter 8.2.2 --- Network Robustness --- p.90Chapter 8.2.3 --- Inference Network Applications --- p.91Chapter 8.2.4 --- Architecture for the Bellman-Ford Algorithm --- p.91Bibliography --- p.92Appendices --- p.99Chapter A --- Detailed Schematic --- p.99Chapter A.1 --- Schematic of the Inference Network Structures --- p.99Chapter A.1.1 --- Unit with Self-Feedback --- p.99Chapter A.1.2 --- Unit with Self-Feedback Removed --- p.100Chapter A.1.3 --- Unit with a Compact Minimizer --- p.100Chapter A.1.4 --- Network Modules --- p.100Chapter A.2 --- Inference Network Interface Circuits --- p.100Chapter B --- Circuit Simulation and Layout Tools --- p.107Chapter B.1 --- Circuit Simulation --- p.107Chapter B.2 --- VLSI Circuit Design --- p.110Chapter B.3 --- VLSI Circuit Layout --- p.111Chapter C --- The Conjugate-Gradient Descent Algorithm --- p.113Chapter D --- Shortest Path Problem on MasPar --- p.11