Out-of-Sequence Prevention for Multicast Input-Queuing Space-Memory-Memory Clos-Network

This paper proposes two cell dispatching algorithms for the input-queuing space-memory-memory (IQ-SMM) Closnetwork to reduce out-of-sequence (OOS) for multicast traffic. The frequent connection pattern change of DSRR results in a severe OOS problem. Based on the principle of DSRR, MFDSRR is able to reduce OOS but still suffers from it under high traffic load. MFRR maintains the connection pattern separately for each input and can eliminate the in-packet OOS and thus significantly reduces the reassembly buffer size and delay

High-radix Packet-Switching Architecture for Data Center Networks

We propose a highly scalable packet-switching architecture that suits for demanding Data center Networks (DCNs). The design falls into the category of buffered multistage switches. It affiliates a three-stage Clos-network and the Networks-on-Chip (NoC) paradigm. We also suggest a congestion-aware routing algorithm that shares the traffic load among the switch's central modules via interleaved connecting links. Unlike conventional switches, the current proposal provides better path diversity, simple scheduling, speedup and robustness to load variation. Simulation results show that the switch is scalable with the portcount and traffic fluctuation, and that it outperforms different switches under many traffic patterns

A New Paradigm to Build Scalable Packet-Switches for Data Center Networks

This paper presents the design, implementation, and evaluation of a class of packet-switching fabric architectures. Based on the well-investigated three-stage Clos-network, we propose a variety of packet-switches that are constructed by adding the most beneficial Network-on-Chip (NoC) paradigm which offers many distinct and practical advantages. Compared to the conventional crossbar switches, the NoC-based architectures provide better path-diversity, simple packet scheduling and speedup. A gradual design method is adopted to enhance the performance of the NoC switch, and several related issues such as the congestion avoidance, micro level load-balancing, and costeffectiveness are addressed. The NoC switches exhibit a high scalability potential in - both - the port count and traffic volume, making them a good candidate for the next-generation Data Center Networks

Journal of Telecommunications and Information Technology, 2018, nr 1

This paper is devoted to evaluating the performance of Space-Memory-Memory (SMM) Clos-network switches under a packet dispatching scheme employing static connection patterns, referred to as Static Dispatching (SD). The control algorithm with static connection patterns can be easily implemented in the SMM fabric due to bufferless switches in the first stage. Stability is one of the very important performance factors of packet switching nodes. In general, a switch is stable for a particular arrival process if the expected length of the packet queues does not increase without limitation. To prove the stability of the SMM Clos-network switches considered under the SD packet dispatching scheme the discrete Markov chain model of the switch is used and Foster’s criteria to extend Lyapunov’s second (direct) method of stability investigation of discrete time stochastic systems are used. The results of simulation experiments, in terms of average cell delay and packet queue lengths, are shown as well

ESTADO DEL ARTE DE SCHEDULING ALGORITHMS (ALGORITMOS DE PROGRAMACIÓN DE ENVÍO)

El presente artículo presenta un estado del arte de los llamados algoritmos de programación de envío, o en inglés “scheduling algorithms” los cuales determinan el método en que un dispositivo de red envía paquetes al medio de transmisión. Estos algoritmos son importantes para la consecución de calidad de servicio en redes convergentes y la correcta comprensión de ellos es determinante para entender los fenómenos de tráfico y cumplir los requerimientos dados en los diferentes tipos de redes (Ethernet, TDM, WiMAX, Wireless, etc)

Packet Dispatching Schemes for Three-Stage Buffered Clos-Network Switches

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A Scalable Packet-Switch Architecture Based on OQ NoCs for Data Center Networks

Data Center switches need guarantee high throughput, resiliency and scalability for large-scale networks with constantly floating requirements. Multistage packet switches have been a pervasive solution to implement high-capacity Data Center Networks (DCNs) switches and routers. Yet, classical multistage switching architectures with their Space-Memory variants have shown limited performance. Most proposals prove either too complex to implement or not cost effective. In this paper, we present a highly scalable packet-switch for the DCN environment, in which we exploit the Network-on-Chip (NoC) design paradigm to replace the single-hop crossbars with multi-hop Switching Elements (SEs). In particular, we describe a three-stage switch with Output-Queued Unidirectional NoCs (OQ-UDN) in the central stage of the Clos-network. The design has several advantages over conventional multistage switches. First, it uses a simple Round-Robin (RR) packet dispatching scheme and avoids the need for complex and costly input modules. Besides, it offers better load balancing, a pipelined scheduling and more path-diversity. We assess the performance of the switch in terms of throughput, end-to-end latency and blocking probability using Markov chain analysis, and we propose an analytical model that integrates the various design parameters. Through extensive simulations, we show that the switching architecture achieves high performance under different types of traffic, and that both the analytical and experimental results correlate over wide range of evaluation settings