Reliable Hardware Architectures for Cyrtographic Block Ciphers LED and HIGHT

Cryptographic architectures provide different security properties to sensitive usage models. However, unless reliability of architectures is guaranteed, such security properties can be undermined through natural or malicious faults. In this thesis, two underlying block ciphers which can be used in authenticated encryption algorithms are considered, i.e., LED and HIGHT block ciphers. The former is of the Advanced Encryption Standard (AES) type and has been considered areaefficient, while the latter constitutes a Feistel network structure and is suitable for low-complexity and low-power embedded security applications. In this thesis, we propose efficient error detection architectures including variants of recomputing with encoded operands and signature-based schemes to detect both transient and permanent faults. Authenticated encryption is applied in cryptography to provide confidentiality, integrity, and authenticity simultaneously to the message sent in a communication channel. In this thesis, we show that the proposed schemes are applicable to the case study of Simple Lightweight CFB (SILC) for providing authenticated encryption with associated data (AEAD). The error simulations are performed using Xilinx ISE tool and the results are benchmarked for the Xilinx FPGA family Virtex- 7 to assess the reliability capability and efficiency of the proposed architectures

Методы функционального диагностирования ошибок шифрования в симметричных криптографических системах

Проведено аналіз існуючих рішень з виявлення несправностей та помилок у симетричних криптографічних системах. Розглянуто аналітичну модель поширення помилок. Запропоновано узагальнену методику діагностування помилок шифрування, яка базується на спільних операціях, які використовуються у більшості криптографічних алгоритмів.Known issues analysis of symmetric cryptographic systems fault detection is carried out. Analytic model for error coverage is considered. Generalized procedure for enciphering fault detection based on commonly used operations from most cryptographic algorithms is proposed

An embedded sensor node microcontroller with crypto-processors

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed

Impeccable Circuits

By injecting faults, active physical attacks pose serious threats to cryptographic hardware where Concurrent Error Detection (CED) schemes are promising countermeasures. They are usually based on an Error-Detecting Code (EDC) which enables detecting certain injected faults depending on the specification of the underlying code. Here, we propose a methodology to enable correct, practical, and robust implementation of code-based CEDs. We show that straightforward hardware implementations of given code-based CEDs can suffer from severe vulnerabilities, not providing the desired protection level. In particular, propagation of faults into combinatorial logic is often ignored in security evaluation of these schemes. First, we formally define this detrimental effect and demonstrate its destructive impact. Second, we introduce an implementation strategy to limit the fault propagation effect. Third, in contrast to many other works where the fault coverage is the main focus, we present a detailed implementation strategy which can guarantee the detection of any fault covered by the underlying EDC. This holds for any time of the computation and any location in the circuit, both in data processing and control unit. In short, we provide practical guidelines how to construct efficient CED schemes with arbitrary EDCs to achieve the desired protection level. We practically evaluate the efficiency of our methodology by case studies covering different symmetric block ciphers and various linear EDCs

On a Side Channel and Fault Attack Concurrent Countermeasure Methodology for MCU-based Byte-sliced Cipher Implementations

As IoT applications are increasingly being deployed, there comes along an ever increasing need for the security and privacy of the involved data. Since cryptographic implementations are used to achieve these goals, it is important for embedded software developers to take into consideration hardware attacks. Side Channel Analysis (SCA) and Fault Attacks (FA) are the main classes of such attacks, which can either reduce or even eliminate the security levels of an em-bedded design. Therefore, cryptographic implementations must address both of them at the same time. To this end, multiple solutions have been proposed to address both attacks in one solution, such as Dual Pre-charge Logic (DPL) and Encoding countermeasures. In this work, we discuss the advantages and disadvantages of the state of the art, concurrent SCA and FA countermeasures. Additionally, we propose a software countermeasure in order to provide protection against both types of attacks. The proposed countermeasure is a general approach, applicable to any byte-sliced cipher and any modern MCUs (32- and 64-bit). The proposed countermeasure is ap-plied to an AES S-BOX implementation, for a 32-bit MCU (ARM Cortex-M3). The countermeasure has been experimen-tally evaluated against Correlation Power Analysis (CPA) attacks for both platforms while its fault detection capabilities are theoretically described

Authentication In Wireless Sensor Networks

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2005Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2005Bu çalışmada önerilmiş veya gerçekleştirilmiş kablosuz duyarga ağları asıllama protokolleri incelenmiş ve ayrıntılarıyla açıklanmıştır. Bu protokollerin olumlu ve olumsuz yanları incelenmiş ve bazı karşılaştırmalar yapılmıştır. Son olarak, tamamıyla gerçeklenmiş olan ilk kablosuz duyarga ağları veri bağı katmanı asıllama protokolü TinySec incelenmiştir. TinySec alınan mesajların asıllanabilmesi için mesajların sonuna kapalı anahtarla hesaplanan ve bir şifreleme algoritmasına dayanan mesaj asıllama kodu eklemektedir. Bu çalışmada mesaj asıllama kodu hesaplanmasında kullanılan şifreleme algoritması ve altyapı değiştirilerek, performans karşılaştırılması yapılmıştır. RC5 ve Skipjack algoritmaları kullanılarak yapılan karşılaştırmalarda RC5 ile yapılan asıllamanın daha hızlı olduğu ve daha az güç tükettiği sonucuna varılmıştır.In this study, a broad range of on going research efforts in authentication within the wireless sensor networks are described in detail. Advantages and disadvantages of the proposed systems are described and some comparisons are made. Finally, TinySec which is said to be the first fully implemented link layer security architecture for wireless sensor networks is discussed. TinySec uses message authentication codes for authentication which are formed by secure hash functions and an encryption algorithm. In this thesis TinySec’s underlying authentication and encryption mechanism is changed and compared by using two different encryption algorithms which are RC5 and Skipjack. It is seen that using RC5 for authentication within TinySec is slightly faster than using Skipjack and it consumes less power.Yüksek LisansM.Sc