93 research outputs found
Automatic synthesis and optimization of partially specified asynchronous systems
A method for automating the synthesis of asynchronous control circuits from high level (CSP-like) and/or partial STG (involving only functionally critical events) specifications is presented. The method solves two key subtasks in this new, more flexible, design flow: handshake expansion, i.e. inserting reset events with maximum concurrency, and event reshuffling under interface and concurrency constraints, by means of concurrency reduction. In doing so, the algorithm optimizes the circuit both for size and performance. Experimental results show a significant increase in the solution space explored when compared to existing CSP-based or STG-based synthesis tools.Peer ReviewedPostprint (author's final draft
Structural Decomposition of STGs
Specification of asynchronous circuit behaviour becomes more complex as the
complexity of today’s System-On-a-Chip (SOC) design increases. This also causes
the Signal Transition Graphs (STGs) – interpreted Petri nets for the specification
of asynchronous circuit behaviour – to become bigger and more complex, which
makes it more difficult, sometimes even impossible, to synthesize an asynchronous
circuit from an STG with a tool like petrify [CKK+96] or CASCADE [BEW00].
It has, therefore, been suggested to decompose the STG as a first step; this
leads to a modular implementation [KWVB03] [KVWB05], which can reduce syn-
thesis effort by possibly avoiding state explosion or by allowing the use of library
elements. A decomposition approach for STGs was presented in [VW02] [KKT93]
[Chu87a]. The decomposition algorithm by Vogler and Wollowski [VW02] is based
on that of Chu [Chu87a] but is much more generally applicable than the one in
[KKT93] [Chu87a], and its correctness has been proved formally in [VW02].
This dissertation begins with Petri net background described in chapter 2.
It starts with a class of Petri nets called a place/transition (P/T) nets. Then
STGs, the subclass of P/T nets, is viewed. Background in net decomposition
is presented in chapter 3. It begins with the structural decomposition of P/T
nets for analysis purposes – liveness and boundedness of the net. Then STG
decomposition for synthesis from [VW02] is described.
The decomposition method from [VW02] still could be improved to deal with
STGs from real applications and to give better decomposition results. Some
improvements for [VW02] to improve decomposition result and increase algorithm
efficiency are discussed in chapter 4. These improvement ideas are suggested in
[KVWB04] and some of them are have been proved formally in [VK04].
The decomposition method from [VW02] is based on net reduction to find
an output block component. A large amount of work has to be done to reduce
an initial specification until the final component is found. This reduction is not
always possible, which causes input initially classified as irrelevant to become
relevant input for the component. But under certain conditions (e.g. if structural
auto-conflicts turn out to be non-dynamic) some of them could be reclassified as
irrelevant. If this is not done, the specifications become unnecessarily large, which
intern leads to unnecessarily large implemented circuits. Instead of reduction, a
new approach, presented in chapter 5, decomposes the original net into structural
components first. An initial output block component is found by composing the
structural components. Then, a final output block component is obtained by net
reduction.
As we cope with the structure of a net most of the time, it would be useful
to have a structural abstraction of the net. A structural abstraction algorithm
[Kan03] is presented in chapter 6. It can improve the performance in finding an
output block component in most of the cases [War05] [Taw04]. Also, the structure
net is in most cases smaller than the net itself. This increases the efficiency of the
decomposition algorithm because it allows the transitions contained in a node of
the structure graph to be contracted at the same time if the structure graph is
used as internal representation of the net.
Chapter 7 discusses the application of STG decomposition in asynchronous
circuit design. Application to speed independent circuits is discussed first. Af-
ter that 3D circuits synthesized from extended burst mode (XBM) specifications
are discussed. An algorithm for translating STG specifications to XBM specifi-
cations was first suggested by [BEW99]. This algorithm first derives the state
machine from the STG specification, then translates the state machine to XBM
specification. An XBM specification, though it is a state machine, allows some
concurrency. These concurrencies can be translated directly, without deriving
all of the possible states. An algorithm which directly translates STG to XBM
specifications, is presented in chapter 7.3.1. Finally DESI, a tool to decompose
STGs and its decomposition results are presented
Verification and synthesis of asynchronous control circuits using petri net unfoldings
PhD ThesisDesign of asynchronous control circuits has traditionally been associated with application of
formal methods. Event-based models, such as Petri nets, provide a compact and easy to
understand way of specifying asynchronous behaviour. However, analysis of their behavioural
properties is often hindered by the problem of exponential growth of reachable state space.
This work proposes a new method for analysis of asynchronous circuit models based on Petri
nets. The new approach is called PN-unfolding segment. It extends and improves existing
Petri nets unfolding approaches. In addition, this thesis proposes a new analysis technique
for Signal Transition Graphs along with an efficient verification technique which is also based
on the Petri net unfolding. The former is called Full State Graph, the latter - STG-unfolding
segment. The boolean logic synthesis is an integral part of the asynchronous circuit design
process. In many cases, even if the verification of an asynchronous circuit specification has
been performed successfully, it is impossible to obtain its implementation using existing methods
because they are based on the reachability analysis. A new approach is proposed here
for automated synthesis of speed-independent circuits based on the STG-unfolding segment
constructed during the verification of the circuit's specification. Finally, this work presents
experimental results showing the need for the new Petri net unfolding techniques and confirming
the advantages of application of partial order approach to analysis, verification and
synthesis of asynchronous circuits.The Research Committee, Newcastle University:
Overseas Research Studentship Award
Qualitatively modelling genetic regulatory networks : Petri net techniques and tools
The development of post-genomic technologies has led to a paradigm shift in the way we study genetic regulatory networks (GRNs) - the underlying systems which mediate cell function. To complement this, the focus is on devising scalable, unambiguous and automated formal techniques for holistically modelling and analysing these complex systems. Quantitative approaches offer one possible solution, but do not appear to be commensurate with currently available data. This motivates qualitative approaches such as Boolean networks (BNs) , which abstractly model the system without requiring such a high level of data completeness. Qualitative approaches enable fundamental dynamical properties to be studied, and are well-suited to initial investigations. However, strengthened formal techniques and tool support are required if they are to meet the demands of the biological community. This thesis aims to investigate, develop and evaluate the application of Petri nets (PNs) for qualitatively modelling and analysing GRNs. PNs are well-established in the field of computer science, and enjoy a number of attractive benefits, such a wide range of techniques and tools, which make them ideal for studying biological systems. We take an existing qualitative PN approach for modelling GRNs based on BNs, and extend it to more general models based on multi-valued networks (MVNs). Importantly, we develop tool support to automate model construction. We illustrate our approach with two detailed case studies on Boolean models for carbon stress in Escherichia coli and sporulation in Bacillus subtilis, and then consider a multi-valued model of the former. These case studies explore the analysis power of PN s by exploiting a range of techniques and tools. A number of behavioural differences are identified between the two E. coli models which lead us to question their formal relationship. We investigate this by proposing a framework for reasoning about the behaviour of MVNs at different levels of abstraction. We develop tool support for practical models, and show a number of important results which motivate the need for multi-valued modelling. Asynchronous BN s can be seen to be more biologically realistic than their synchronous counterparts. However, they have the drawback of capturing behaviour which is unrealisable in practice. We propose a novel approach for refining such behaviour using signal transition graphs, a PN formalism from asynchronous circuit design. We automate our approach, and demonstrate it using a BN of the lysis-lysogeny switch in phage A. Our results show that a more realistic asynchronous model can be derived which preserves the stochastic switch.EThOS - Electronic Theses Online ServiceGBUnited Kingdo
Multi-resource approach to asynchronous SoC : design and tool support
As silicon cost reduces, the demands for higher performance and lower power consumption are ever increasing. The ability to dynamically control the number of resources employed can help balance and optimise a system in terms of its throughput, power consumption, and resilience to errors. The management of multiple resources requires building more advanced resource allocation logic than traditional 1-of-N arbiters posing the need for the efficient design flow supporting both the design and verification of such systems. Networks-on-Chip provide a good application example of distributed arbitration, in which the processor cores needing to transmit data are the clients; and the point-to-point links are the resources managed by routers. Building fast and smart arbiters can greatly benefit such systems in providing efficient and reliable communication service. In this thesis, a multi-resource arbiter was developed based on the Signal Transition Graph (STG) development flow. The arbiter distributes multiple active interchangeable resources that initiate requests when they are ready to be used. It supports concurrent resource utilization, which benefits creating asynchronous Multiple-Input-Multiple- Output (MIMO) queues. In order to deal with designs of higher complexity, an arbiter-oriented design flow is proposed. The flow is based on digital circuit components that are represented internally as STGs. This allows designing circuits without directly working with STGs but allowing their use for synthesis and formal verification. The interfaces for modelling, simulation, and visual model representation of the flow were implemented based on the existing modelling framework. As a result, the verification phase of the flow has helped to find hazards in existing Priority arbiter implementations. Finally, based on the logic-gate flow, the structure of a low-latency general purpose arbiter was developed. This design supports a wide variety of arbitration problems including the multi-resource management, which can benefit building NoCs employing complex and adaptive routing techniques.EThOS - Electronic Theses Online ServiceEPSRC grant GR/E044662/1 (STEP)GBUnited Kingdo
Exploiting robustness in asynchronous circuits to design fine-tunable systems
PhD ThesisRobustness property in a circuit defines its tolerance to the effects of process, voltage and
temperature variations. The mode signaling and event communication between computing
units in a asynchronous circuits makes them inherently robust. The level of robustness
depends on the type of delay assumptions used in the design and specification process.
In this thesis, two approaches to exploiting robustness in asynchronous circuits to design
self-adapting and fine-tunable systems are investigated. In the first investigation, a Digitally
Controllable Oscillator (DCO) and a computing unit are integrated such that the operating
conditions of the computing unit modulated the operation of the DCO. In this investigation,
the computing unit which is a self-timed counter interacts with the DCO in a four-phase
handshake protocol. This mode of interaction ensures a DCO and computing unit system
that can fine-tune its operation to adapt to the effects of variations. In this investigation, it
is shown that such a system will operate correctly in wide range of voltage supply. In the
second investigation, a Digital Pulse-Width Modulator (DPWM) with coarse and fine-tune
controls is designed using two Kessels counters. The coarse control of the DPWM tuned the
pulse ratio and pulse frequency while the fine-tune control exploited the robustness property
of asynchronous circuits in an addition-based delay system to add or subtract delay(s) to
the pulse width while maintaining a constant pulse frequency. The DPWM realized gave
constant duty ratio regardless of the operating voltage. This type of DPWM has practical
application in a DC-DC converter circuit to tune the output voltage of the converter in high
resolution. The Kessels counter is a loadable self-timed modulo−n counter, which is realized
by decomposition using Horner’s method, specified and verified using formal asynchronous
design techniques. The decomposition method used introduced parallelism in the system by
dividing the counter into a systolic array of cells, with each cell further decomposed into
two parts that have distinct defined operations. Specification of the decomposed counter cell
parts operation was in three stages. The first stage employed high-level specification using
Labelled Petri nets (LPN). In this form, functional correctness of the decomposed counter is
modelled and verified. In the second stage, a cell part is specified by combing all possible
operations for that cell part in high-level form. With this approach, a combination of inputs
from a defined control block activated the correct operation for a cell part. In the final stage,
the LPNs were converted to Signal Transition Graphs, from which the logic circuits of the
cells were synthesized using the WorkCraft Tool. In this thesis, the Kessels counter was
implemented and fabricated in 350 nm CMOS Technology.Niger Delta Development Commission (NDD
Design And Synthesis Of Clockless Pipelines Based On Self-resetting Stage Logic
For decades, digital design has been primarily dominated by clocked circuits. With larger scales of integration made possible by improved semiconductor manufacturing techniques, relying on a clock signal to orchestrate logic operations across an entire chip became increasingly difficult. Motivated by this problem, designers are currently considering circuits which can operate without a clock. However, the wide acceptance of these circuits by the digital design community requires two ingredients: (i) a unified design methodology supported by widely available CAD tools, and (ii) a granularity of design techniques suitable for synthesizing large designs. Currently, there is no unified established design methodology to support the design and verification of these circuits. Moreover, the majority of clockless design techniques is conceived at circuit level, and is subsequently so fine-grain, that their application to large designs can have unacceptable area costs. Given these considerations, this dissertation presents a new clockless technique, called self-resetting stage logic (SRSL), in which the computation of a block is reset periodically from within the block itself. SRSL is used as a building block for three coarse-grain pipelining techniques: (i) Stage-controlled self-resetting stage logic (S-SRSL) Pipelines: In these pipelines, the control of the communication between stages is performed locally between each pair of stages. This communication is performed in a uni-directional manner in order to simplify its implementation. (ii) Pipeline-controlled self-resetting stage logic (P-SRSL) Pipelines: In these pipelines, the communication between each pair of stages in the pipeline is driven by the oscillation of the last pipeline stage. Their communication scheme is identical to the one used in S-SRSL pipelines. (iii) Delay-tolerant self-resetting stage logic (D-SRSL) Pipelines: While communication in these pipelines is local in nature in a manner similar to the one used in S-SRL pipelines, this communication is nevertheless extended in both directions. The result of this bi-directional approach is an increase in the capability of the pipeline to handle stages with random delay. Based on these pipelining techniques, a new design methodology is proposed to synthesize clockless designs. The synthesis problem consists of synthesizing an SRSL pipeline from a gate netlist with a minimum area overhead given a specified data rate. A two-phase heuristic algorithm is proposed to solve this problem. The goal of the algorithm is to pipeline a given datapath by minimizing the area occupied by inter-stage latches without violating any timing constraints. Experiments with this synthesis algorithm show that while P-SRSL pipelines can reach high throughputs in shallow pipelines, D-SRSL pipelines can achieve comparable throughputs in deeper pipelines
Recent advances in petri nets and concurrency
CEUR Workshop Proceeding
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