Physical Parameter Based Model for Characteristic Impedance of SWCNT Interconnects and its Performance Analysis

Single walled carbon nanotubes (SWCNTs) have been identified as a possible replacement for copper interconnects due to their magnificent electrical and material properties. A series of performance predictions of these interconnects have been done in the last decade. Even then none of the literatures have been provided compact expression for characteristic impedance (Zo) in terms of physical parameters of SWCNT interconnects. A simplified representation of characteristic impedance and the analyze the transient behavior under different mismatch conditions will enable the chip designer to optimize the performance of total circuitry. These studies give an overview of safe amount of load mismatch that can be tolerated by different lengths of interconnects without causing any signal reliability issues. Keywords: SWCNTs, CNT Interconnects, characteristic impedance, transient response, frequency response, load mismatc

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Electrical Transport Modeling of Graphene-Based Interconnects

Due to the downscaling in the design of modern ICs, copper interconnects reach their limitations such as delay, power dissipation, and electromigration. However, a new era of discovered materials, including carbon nanotube, graphene nanoribbon (GNR), and their composite, has been proposed as promising alternatives for interconnect applications. The purpose of this review is to give an overview of the various approaches that are used to model graphene-based interconnects. In this work we focus on why opting for graphene-based interconnect properties as an alternative for copper interconnect replacement; what are the deep theories, which are explaining the electrical transport on those interconnects; and what are the electrical models that are used to model the various kind of graphene-based interconnects

Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond

The limitations of the conventional Cu/low-k interconnect technology for use in future ultra-scaled integrated circuits down to 7 nm in the year 2020 are investigated from the power/performance point of view. Compact models are used to demonstrate the impacts of various interconnect process parameters, for instance, the interconnect barrier/liner bilayer thickness and aspect ratio, on the design and optimization of a multilevel interconnect network. A framework to perform a sensitivity analysis for the circuit behavior to interconnect process parameters is created for future FinFET CMOS technology nodes. Multiple predictive cell libraries down to the 7‒nm technology node are constructed to enable early investigation of the electronic chip performance using commercial electronic design automation (EDA) tools with real chip information. Findings indicated new opportunities that arise for emerging novel interconnect technologies from the materials and process perspectives. These opportunities are evaluated based on potential benefits that are quantified with rigorous circuit-level simulations and requirements for key parameters are underlined. The impacts of various emerging interconnect technologies on the performances of emerging devices are analyzed to quantify the realistic circuit- and system-level benefits that these new switches can offer.Ph.D

Performance analysis of fault-tolerant nanoelectronic memories

Performance growth in microelectronics, as described by Moore’s law, is steadily approaching its limits. Nanoscale technologies are increasingly being explored as a practical solution to sustaining and possibly surpassing current performance trends of microelectronics. This work presents an in-depth analysis of the impact on performance, of incorporating reliability schemes into the architecture of a crossbar molecular switch nanomemory and demultiplexer. Nanoelectronics are currently in their early stages, and so fabrication and design methodologies are still in the process of being studied and developed. The building blocks of nanotechnology are fabricated using bottom-up processes, which leave them highly susceptible to defects. Hence, it is very important that defect and fault-tolerant schemes be incorporated into the design of nanotechnology related devices. In this dissertation, we focus on the study of a novel and promising class of computer chip memories called crossbar molecular switch memories and their demultiplexer addressing units. A major part of this work was the design of a defect and fault tolerance scheme we called the Multi-Switch Junction (MSJ) scheme. The MSJ scheme takes advantage of the regular array geometry of the crossbar nanomemory to create multiple switches in the fabric of the crossbar nanomemory for the storage of a single bit. Implementing defect and fault tolerant schemes come at a performance cost to the crossbar nanomemory; the challenge becomes achieving a balance between device reliability and performance. We have studied the reliability induced performance penalties as they relate to the time (delay) it takes to access a bit, and the amount of power dissipated by the process. Also, MSJ was compared to the banking and error correction coding fault tolerant schemes. Studies were also conducted to ascertain the potential benefits of integrating our MSJ scheme with the banking scheme. Trade-off analysis between access time delay, power dissipation and reliability is outlined and presented in this work. Results show the MSJ scheme increases the reliability of the crossbar nanomemory and demultiplexer. Simulation results also indicated that MSJ works very well for smaller nanomemory array sizes, with reliabilities of 100% for molecular switch failure rates in the 10% or less range

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Surface-bound nanostructures:mechanical and metrological studies

This thesis looks at surface-bound nanowires and nanoparticles, the mechanical and the metrological properties of which are of practical importance in the realization of nanometer-scale electronics. Atomic force microscope (AFM) was the main instrument of research. By bending suspended carbon nanotube structures with the AFM, the Young's modulus of carbon nanotubes has been measured. An efficient new technique that involves an ac-dielectrophoresis preparation of carbon nanotubes on v-groove GaAs substrates and a force-curve measurement of the stiffness has been devised. The Young's modulus of a batch of multiwall carbon nanotubes grown by a single chemical vapor deposition (CVD) process shows a strong diameter dependence, indicating that the small catalyst particles produce crystalline tubes, while the thicker particles produce low-quality tubes with an abundance of structural defects. The experimental result is a strong evidence for the metastable-catalyst growth model of carbon nanotubes in CVD — the growth kinetics of carbon nanotubes is determined by the catalyst's liquid skin, which is more stable for smaller catalysts. As the nanotube study highlighted the importance of the size of catalyst nanoparticles, the topic of accurate nanoparticle sizing by dynamic AFM was then investigated. The measured size of a surface-bound nanoparticle was found to vary with imaging parameters, and a theoretical modeling showed that the non-contact — intermittent-contact mode switching can lead to discrepancies. Experimental results confirmed that the mode switching indeed causes the largest error in size measurements. A discrepancy also exists between the all-non-contact-mode and all-intermittent-contact-mode cases, and this anomaly could be explained by the effects of particle-substrate deformation and capillary forces. Nanoparticles were prepared on surfaces by boiling colloid drops on hot surfaces, a new technique developed for the uniformly dispersed deposition of colloidal nanoparticles and nanowires. Our experiments suggest that the actual deposition occurs through the smooth dewetting of liquid microdrops at elevated temperatures. The method is applicable on a wide range of surfaces and materials. Finally, a general haptic interface for the AFM was realized. The interface can be implemented on different AFM models with little effort, and it supports both the contact- and dynamic-AFM operations. Manipulation of gold nanoparticles has been carried out by raster scanning at different dynamic AFM setpoints, a promising approach for a quantitative study of the nanoparticle-substrate friction